- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16215 > SI3232DC0-EVB (Silicon Laboratories Inc)DAUGHTER CARD W/SI3200 INTERFACE PDF資料下載
參數(shù)資料
| 型號： | SI3232DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 62/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3232 |
| 已供物品： | 板，CD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當(dāng)前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Si3232
Preliminary Rev. 0.96
39
Not
Recommended
fo
r N
ew
D
esi
gn
s
In addition to the variable frequency and amplitude,
there is a selectable dc offset (VOFF) that can be added
to the waveform. The dc offset is defined in the RINGOF
RAM location. The ringing generator has two timers
which allow on/off cadence settings up to 8 s on/8 s off.
In addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
To
initiate
ringing,
the
user
must
program
the
RINGFREQ,
RINGAMP,
and
RINGPHAS
RAM
addresses as well as the RINGTA, and RINGTI
registers, and select the ringing waveshape and dc
offset. Once this is done, the TAEN and TIEN bits are
set as desired. Ringing state is invoked by a write to the
linefeed register. At the expiration of RINGTA, the
Si3232 turns off the ringing waveform and goes to the
on-hook transmission state. At the expiration of RINGTI,
ringing is initiated again. This process continues as long
as the two timers are enabled and the linefeed register
remains in the ringing state.
4.6.2. Internal Trapezoidal Ringing
In
addition
to
the
traditional
sinusoidal
ringing
waveform, the Si3232 can generate a trapezoidal
ringing waveform similar to the one illustrated in
The
RINGFREQ,
RINGAMP,
and
RINGPHAS RAM locations are used for programming
the ringing wave shape as follows:
RINGPHAS = 4 x Period x 8000
RINGAMP = (Desired V/160.8 V) x (215)
RINGFREQ = (2 x RINGAMP) / (tRISE x 8000)
RINGFREQ is a value that is added or subtracted from
the waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
where
So, for a 90 VPK, 20 Hz trapezoidal waveform with a
crest factor of 1.3, the period is 0.05 s, and the rise time
requirement is 0.015 s.
RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640)
RINGAMP = 90/160.8 x (215) = 18340 (0x47A5)
RINGFREQ = (2 x RINGAMP) (0.0153 x 8000) =
300 (0x012C)
The time registers and interrupts described in the
sinusoidal ring description also apply to the trapezoidal
ring waveform.
4.7. Internal Unbalanced Ringing
The Si3232 also provides the ability to generate a
traditional battery-backed unbalanced ringing waveform
for ringing terminating devices that require a high dc
content or for use in ground-start systems that cannot
tolerate a ringing waveform on both the TIP and RING
leads. The unbalanced ringing scheme applies the
ringing signal to the RING lead; the TIP lead remains at
the programmed VCM voltage that is very close to
ground. A programmable dc offset can be preset to
provide dc current for ring trip detection. Figure 18
illustrates the internal unbalanced ringing waveform.
Figure 18. Internal Unbalanced Ringing
To enable unbalanced ringing, set the RINGUNB bit of
the RINGCON register. As is the case with internal
balanced ringing, the unbalanced ringing waveform is
generated by using the on-chip ringing tone generator.
The tone generator used to generate ringing tones is a
two-pole resonator with programmable frequency and
amplitude. Since ringing frequencies are low compared
to the audio band signaling frequencies, the ringing
waveform is generated at a 1 kHz rate.
The ringing generator is programmed via the RINGAMP,
RINGFREQ, and RINGPHAS registers. The RINGOF
register is used to set the dc offset position around
RINGAMP
1
4
---
.00789
1.99211
---------------------
2
15
85
160.173
---------------------
273
0x111
=
t
RISE
3
4
---T1
1
CF
2
-----------
–
=
TPeriod
1
f
RING
--------------
CF
desired crest factor
=
==
RING
TIP
VRING
Si3232
DC Offset
GND
VTIP
VRING
VBATR
-80V
VOVRING
V
CM
DC Offset
VOFF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPZ2D391MHD | CAP ALUM 390UF 200V 20% RADIAL |
| SI3230PPQX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
| M3UFK-1636R | IDC CABLE - MKS16K/MC16M/MCF16K |
| A3RRB-1018G | IDC CABLE - APR10B/AE10G/APR10B |
| SI3225PPTX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3232DCX-EVB | 功能描述:子卡和OEM板 Si3232 DAUGHTER CARD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI3232-FQ | 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-FQR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3232-G-FQ | 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-G-FQR | 功能描述:電信線路管理 IC Dual-CH SLIC only Internal 65 Vrms RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。