參數(shù)資料
型號(hào)： SI3232DCX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 60/128頁
文件大?。?/td> 0K
描述： DAUGHTER CARD W/DISCRETE INTRFC
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3232
已供物品： 板，CD
Si3232
Preliminary Rev. 0.96
37
Not
Recommended
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4.6. Ringing Generation
The Si3232 is designed to provide a balanced ringing
waveform with or without dc offset. The ringing
frequency, cadence, waveshape, and dc offset are all
register-programmable.
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING lines using ringing
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand only half the total ringing amplitude
seen across TIP-RING.
Figure 16. Balanced Ringing Waveform and
Components
The purpose of an internal ringing scheme is to provide
>40 Vrms into a 5 REN load at the terminal equipment
using a user-provided ringing battery supply. The
specific ringing supply voltage required depends on the
ringing voltage desired.
The ringing amplitude at the terminal equipment
depends on the loop impedance as well as the load
impedance in REN. The following equation can be used
to determine the TIP-RING ringing amplitude required
for a specific load and loop condition.
Figure 17. Simplified Loop Circuit During
Ringing
where
When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200 and may require
additional airflow or a modified PCB layout to maintain
acceptable
operating
temperatures.
The
Si3232
automatically applies and removes the ringing signal
during VOC-crossing periods to reduce noise and
crosstalk to adjacent lines. Table 23 provides a list of
registers required for internal ringing generation.
RING
TIP
V
RING
V
TIP
SLIC
V
OFF
GND
V
TIP
V
RING
V
BATH
V
PK
V
OV
V
CM
V
OFF
R
LOOP
V
RING
R
LOAD
V
TERM
+
–
R
OUT
V
TERM
V
RING
R
LOAD
R
LOAD
R
LOOP
R
OUT
++
----------------------------------------------------------------
=
R
LOOP
0.09
per foot for 26 AWG wire
=
R
OUT
320
=
R
LOAD
7000
#REN
--------------------
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI3232-FQ 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3232-FQR 制造商:Silicon Laboratories Inc 功能描述:
SI3232-G-FQ 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3232-G-FQR 功能描述:電信線路管理 IC Dual-CH SLIC only Internal 65 Vrms RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3232-G-GQ 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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