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參數(shù)資料
型號: SI3232DCX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 88/128頁
文件大小: 0K
描述: DAUGHTER CARD W/DISCRETE INTRFC
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3232
已供物品: 板,CD
Si3232
62
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
32
PMTIHI
Pulse Metering Oscillator
Inactive Timer—
High Byte
PULSETI[15:8]7
Init
R/W
0x00
31
PMTILO
Pulse Metering Oscillator
Inactive Timer—
Low Byte
PULSETI[7:0]7
Init
R/W
0x00
Polarity Reversal
7
POLREV
Polarity Reversal Settings
POLREV4
VOCZERO
PREN
RAMP
Init
R/W
RAM Access
103
RAMADDR
RAM Address
RAMADDR[7:0]
Oper
R/W
0x00
102
RAMDATHI
RAM Data—
High Byte
RAMDAT[15:8]
Oper
R/W
0x00
101
RAMDATLO
RAM Data—
Low Byte
RAMDAT[7:0]
Oper
R/W
0x00
4
RAMSTAT
RAM Address Status
RAMSTAT4
Init
R
0x00
Soft Reset
1
RESET
Soft Reset
RESETB
RESETA
Init
R/W
0x00
Ringing
23
RINGCON
Ringing Configuration
ENSYNC4
RDACEN4
RINGUNB
TAEN
TIEN
RINGEN4
UNBPOLR
TRAP
Init
R/W
0x00
25
RINGTAHI
Ringing Oscillator
Active Timer—High Byte
RINGTA[15:8]
Init
R/W
0x00
24
RINGTALO
Ringing Oscillator
Active Timer—Low Byte
RINGTA[7:0]
Init
R/W
0x00
27
RINGTIHI
Ringing Oscillator
Inactive Timer—High Byte
RINGTI[15:8]
Init
R/W
0x00
26
RINGTILO
Ringing Oscillator
Inactive Timer—Low Byte
RINGTI[7:0]
Init
R/W
0x00
Relay Configuration
5
RLYCON
Relay Driver and
Battery Switching
Configuration
BSEL5
RRAIL
RDOE
GPO
Diag
R/W
0x00
SLIC Bias Control
8
SBIAS
SLIC Bias Control
STDBY5
SQLCH5
CAPB5
BIASEN5
OBIAS[1:0]5
ABIAS[1:0]5
Init
R/W
0xE0
Si3200 Thermometer
72
THERM
Si3200 Thermometer
STAT4
SEL5
Oper
R/W
0x45
Impedance Synthesis Coefficients
33
ZRS
Impedance Synthesis
Analog Real Coeff
RS[3:0]6
Init
R/W
0x00
34
ZZ
Impedance Synthesis
Analog Complex Coeff
ZSDIS6
ZSOHT6
ZP[1:0]6
ZZ[1:0]6
Init
R/W
0x00
Reg
Addr3
Mnemonic
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
Def.
Hex
Notes:
1.
Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the
PLL is not locked (MSTRSTAT[PLOCK]).
2.
Reserved bit values are indeterminate.
3.
Register address is in decimal.
4.
Read only.
5.
Protected bits.
6.
Per-channel bit(s).
7.
Si3220 only.
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