- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16215 > SI3232DCX-EVB (Silicon Laboratories Inc)DAUGHTER CARD W/DISCRETE INTRFC PDF資料下載
參數(shù)資料
| 型號： | SI3232DCX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 73/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/DISCRETE INTRFC |
| 標準包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3232 |
| 已供物品： | 板，CD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Si3232
Preliminary Rev. 0.96
49
Not
Recommended
fo
r N
ew
D
esi
gn
s
The resulting gain levels using the ARX stage are
summarized in Table 30. All settings assume an
external codec with 475
per leg of source impedance
driving the RX inputs differentially at VRXPa-VRXNa
(for channel a) or VRXPb-VRXNb (for channel b) to
achieve a 0 dBm0 TIP-RING audio output signal.
4.15. System Clock Generation
The Si3232 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256kHz, 512kHz, 786kHz,
1.024 MHz,
1.536 MHz,
1.544 MHz,
2.048 MHz,
4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The 3-bit ratio information is automatically
transferred
into
an
internal
register,
PLL_MULT,
following a device reset. PLL_MULT is used to control
the internal PLL, which multiplies PCLK as needed to
generate the rate required to run the internal filters and
other circuitry.
The PLL clock synthesizer settles quickly after powerup
or update of the PLL-MULT register. The PLL lock
process begins immediately after the RESET pin is
pulled high and will take approximately 5 ms to achieve
lock after RESET is released with stable PCLK and
FSYNC. However, the settling time depends on the
PCLK frequency and can be predicted based on the
following equation:
tSETTLE =64 / fPCLK
Note: Therefore, the RESET pin must be held low during
powerup and should only be released when both PCLK
and FSYNC signals are known to be stable.
4.15.1. Interrupt Logic
The Si3232 is capable of generating interrupts for the
following events:
Loop current/ring ground detected.
Ground key detected.
Ring trip detected.
Power alarm.
Ringing active timer expired.
Ringing inactive timer expired.
Pulse metering active timer expired.
Pulse metering inactive timer expired.
RAM address access complete.
The interface to the interrupt logic consists of six
registers. Three interrupt status registers (IRQ0–IRQ3)
contain one bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain one bit for each
interrupt function. In the case of the interrupt mask
registers, the bits are active high. Refer to the
appropriate functional description text for operational
details of the interrupt functions.
Figure 26. PLL Frequency Synthesizer
Table 30. ARX Attenuation Stage Settings
ARXMUTE
Setting
ARX[1:0]
Setting
Typical TX Path Gain
1
xx
Mute (no T-R output)
000
0 dB (G = 1)
0
01
–3.52 dB (G = 2/3)
0
10
–6.02 dB (G = 1/2)
0
11
Reserved. Do not use.
PFD
DIV M
PLL_MULT
VCO
÷2
RESET
28.672 MHz
PCLK
相關PDF資料 |
PDF描述 |
|---|---|
| M1AXK-3440K | IDC CABLE - MSC34K/MC34F/X |
| SI3232PPT0-EVB | BOARD EVAL W/SI3200 INTERFACE |
| UPZW6101MHD | CAP ALUM 100UF 420V 20% RADIAL |
| SI3232DC0-EVB | DAUGHTER CARD W/SI3200 INTERFACE |
| UPZ2D391MHD | CAP ALUM 390UF 200V 20% RADIAL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI3232-FQ | 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-FQR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3232-G-FQ | 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-G-FQR | 功能描述:電信線路管理 IC Dual-CH SLIC only Internal 65 Vrms RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-G-GQ | 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。