參數(shù)資料
型號(hào)： SI5315B-C-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 24/54頁
文件大?。?/td> 0K
描述： IC CLOCK MULT 8KHZ-125MHZ 36QFN
應(yīng)用說明： SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝： 490
系列： DSPLL®
類型： 時(shí)鐘/頻率倍增器，抖動(dòng)衰減器，多路復(fù)用器
PLL： 無
主要目的： 以太網(wǎng)，SONET/SDH/PDH，電信
輸入： CML，CMOS，LVDS，LVPECL
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 125MHz
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 托盤
Si5315
30
Rev. 1.0
5.2.5. Hitless Switching with Phase Build-Out
Silicon Laboratories switching technology performs "phase build-out" to minimize the propagation of phase
transients to the clock outputs during input clock switching. All switching between input clocks occurs within the
input multiplexor and phase detector circuitry. The phase detector circuitry continually monitors the phase
difference between each input clock and the DSPLL output clock, fOSC. The phase detector circuitry can lock to a
clock signal at a specified phase offset relative to fOSC so that the phase offset is maintained by the PLL circuitry.
At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for
the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the
new clock's phase offset so that the phase of the output clock is not disturbed. The phase difference between the
two input clocks is absorbed in the phase detector's offset value, rather than being propagated to the clock output.
The switching technology virtually eliminates the output clock phase transients traditionally associated with clock
rearrangement (input clock switching). The Maximum Time Interval Error (MTIE) and maximum slope for clock
output phase transients during clock switching are given in (Table 3, “AC Characteristics”). These values fall
significantly below the limits specified in the ITU-T G.8262, Telcordia GR-1244-CORE, and GR-253-CORE
requirements.
5.3. Input Clock Control
This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless
switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two
clocks differ in frequency by more than 100 ppm.
5.3.1. Manual Clock Selection
Manual control of input clock selection is chosen via the CS_CA pin according to Table 11 and Table 12.
5.3.2. Automatic Clock Selection
The AUTOSEL input pin sets the input clock selection mode as shown in Table 11. Automatic switching is either
revertive or non-revertive. Setting AUTOSEL to M or H, changes the CS_CA pin to an output pin that indicates the
state of the automatic clock selection.
Table 11. Automatic/Manual Clock Selection
AUTOSEL
Clock Selection Mode
L
Manual
M
Automatic non-revertive
H
Automatic revertive
Table 12. Manual Input Clock Selection, AUTOSEL = L
CS_CA
Si5315
AUTOSEL = L
0CKIN1
1CKIN2
Table 13. Clock Active Indicators, AUTOSEL = M or H
CS_CA
Active Clock
0CKIN1
1CKIN2
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參數(shù)描述
SI5315B-C-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl SyncE Clk Xplier/Jitt Attn 2/2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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