參數(shù)資料
型號: SI5315B-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 28/54頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 8KHZ-125MHZ 36QFN
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH/PDH,電信
輸入: CML,CMOS,LVDS,LVPECL
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 125MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5315
34
Rev. 1.0
6. High-Speed I/O
6.1. Input Clock Buffers
The Si5315 provides differential inputs for the CKINn clock inputs. These inputs are internally biased to a common
mode voltage [see Table 2, “DC Characteristics”] and can be driven by either a single-ended or differential source.
Figure 11 through Figure 14 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note
that the jitter generation improves for higher levels on CKINn (within the limits in Table 3, “AC Characteristics”).
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
However, either ac or dc coupling is acceptable. Figures 11 and 12 show various examples of different input
termination arrangements. Unused inputs can be left unconnected.
Figure 11. Differential LVPECL Termination
Figure 12. Single-ended LVPECL Termination
40 k
C
±
CKIN
_
CKIN +
VICM
300
130
3.3 V
82
Si5315
LVPECL
Driver
40 k
40 k
C
CKIN
_
CKIN +
VICM
300
130
3.3 V
82
Si5315
Driver
40 k
±
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SI5315B-C-GMR 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl SyncE Clk Xplier/Jitt Attn 2/2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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