參數(shù)資料
型號: SI5315B-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 36/54頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 8KHZ-125MHZ 36QFN
應用說明: SI5315/17 Crystal Selection AppNote
標準包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復用器
PLL:
主要目的: 以太網,SONET/SDH/PDH,電信
輸入: CML,CMOS,LVDS,LVPECL
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 125MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應商設備封裝: 36-QFN(6x6)
包裝: 托盤
Si5315
Rev. 1.0
41
8. Power Supply Filtering
This device incorporates an on-chip voltage regulator with excellent PSRR to power the device from a supply
voltage of 1.8, 2.5, or 3.3 V. The device requires minimal supply decoupling and no stringent layout or ground plane
islands. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply
voltage directly. Table 3, “AC Characteristics” gives the sensitivity of the on-chip oscillator to changes in the supply
voltage. Refer to the Si5315 evaluation board for an example.
The center ground pad under the device must be electrically and thermally connected to the ground plane.
Figure 22. Typical Power Supply Bypass Network
Figure 23. Fout = 155 MHz with 112 Hz Loop Bandwidth, 100 mVp-p Supply Noise
Si5315
V
DD
GND &
GND Pad
C1 – C3
C
4
Ferrite
Bead
0.1 uF
1.0 uF
System
Power
Supply
(1.8, 2.5, or
3.3 V)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
1
10
100
1000
Frequency of Power Supply Noise (kHz)
Power Supply Noise to Output Transfer Function
Pow
e
rS
u
ppl
y
Noi
se
Rej
ecti
on
Rat
io
(dB)
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相關代理商/技術參數(shù)
參數(shù)描述
SI5315B-C-GMR 功能描述:時鐘發(fā)生器及支持產品 Pin-Ctrl SyncE Clk Xplier/Jitt Attn 2/2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
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