(VDD
參數(shù)資料
型號: SI5315B-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 34/54頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 8KHZ-125MHZ 36QFN
應用說明: SI5315/17 Crystal Selection AppNote
標準包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH/PDH,電信
輸入: CML,CMOS,LVDS,LVPECL
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 125MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5315
4
Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Temperature Range
TA
–40
25
85
C
Supply Voltage
VDD
3.3 V nominal
2.97
3.3
3.63
V
2.5 V nominal
2.25
2.5
2.75
V
1.8 V nominal
1.71
1.8
1.89
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Current (Supply
current is independent of
VDD)
IDD
LVPECL Format
644.53125 MHz Out
All CKOUTs Enabled1
—251
279
mA
LVPECL Format
644.53125 MHz Out
Only 1 CKOUT Enabled1
—217
243
mA
CMOS Format
25.00 MHz Out
All CKOUTs Enabled2
—204
234
mA
CMOS Format
25.00 MHz Out
Only CKOUT1 Enabled2
—194
220
mA
CKINn Input Pins
Input Common Mode Voltage
(Input Threshold Voltage)
VICM
1.8 V ± 5%
0.9
1.4
V
2.5 V ± 10%
1.0
1.7
V
3.3 V ± 10%
1.1
1.95
V
Input Resistance
CKNRIN
Single-ended
20
40
60
k
Input Voltage Level Limits
CKNVIN
0—
VDD
V
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
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