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參數(shù)資料
| 型號(hào)： | SLB128B |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Transmitter with built-in scaler for LVDS Display Interface (LDI) |
| 中文描述： | 發(fā)射器內(nèi)置的LVDS顯示接口（低密度脂蛋白縮放） |
| 文件頁(yè)數(shù)： | 15/48頁(yè) |
| 文件大?。?/td> | 650K |
| 代理商： | SLB128B |
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DS90C2501 Pin Description
(Continued)
Pin Name
OPTION SELECTION
V
REF
Pin No.
I/O Type
Description
83
I-ANALOG
This pin is never to be left floating and never tie to GND.
For LVTTL level data input, tie V
REF
to V
CC
3V. When V
REF
>
1.8V, input data
is set to LVTTL level.
For low voltage swing level data input, tie V
REF
to
1
2
V
DDQ
(V
DDQ
provided by
host interface) V
DDQ
is from the host. When V
REF
<
=1.0V, indicates input
data is in low voltage swing mode.
Input data = logic High = V
REF
+100 mV in low voltage swing level.
Input data = logic Low = V
REF
100 mV in low voltage swing level.
These pins are used in production testing and should be tied to GND in
normal operation.
TST1, TST2,
TST3
POWER (See Application Information for power supply decoupling requirements)
V
CC
/DV
CC
81, 82,
75, 77,
96, 119,
123, 125
GND/DGND
33, 73,
74, 76,
78, 79,
80, 84,
118, 122,
124
V
CC
3V
121, 127
PWR
19, 20, 85
I-LVTTL 2.5
PWR
Power supply pins (pin 75, 77, 81, 82, 96, 119, 123, and 125) for 2.5V LVTTL
inputs and digital circuitry.
PWR
GND or DGND reference for 2.5V TTL inputs and digital circuitry.
The V
CC
3V is required for internal logic and certain 3V I/O.
During power up stage, voltage readings on these pins must be higher than
2.5V pins.
Ground return pins for V
CC
3V powered logic.
GND3V
120, 126,
128
87, 89
PWR
SPLLV
CC
PWR
2.5V power supply pins for scaler PLL circuitry. It is not recommended to
share this power with PLLV
CC
.
Ground returns for scaler PLL circuitry.
2.5V power supply pins for Tx PLL circuitry. It is not recommended to share
this power with SPLLV
CC
.
Ground returns for Tx PLL circuitry.
Power supply pins for LVDS output drivers.
Ground return pins for LVDS output drivers.
3V power supply pins for LVDS output drivers.
During power up stage, voltage readings on these pins must be higher than
2.5V pins.
Ground return pins for 3V LVDS outputs.
SPLLGND
PLLV
CC
86, 88, 90
92, 94
PWR
PWR
PLLGND
LVDSV
CC
LVDSGND
LVDSV
CC
3V
91, 93, 95
105, 109
104, 108
101, 103,
107, 111
PWR
PWR
PWR
PWR
LVDSGND3V
102, 106,
110, 112
PWR
Note 11:
When device power is applied, it is possible for these outputs to switch to a logic “1” momentarily as the 3.3V is rising and before 2.5V reaches at least
0.8V. During this brief period, the pad control logic could be non-deterministic, RESETN will have no effect. It is recommended these outputs are gated externally
if the system design requires them to remain in the inactive logic “0” state during power-on.
D
www.national.com
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