參數(shù)資料
型號： SLB128B
廠商： National Semiconductor Corporation
英文描述： Transmitter with built-in scaler for LVDS Display Interface (LDI)
中文描述： 發(fā)射器內(nèi)置的LVDS顯示接口（低密度脂蛋白縮放）
文件頁數(shù)： 6/48頁
文件大?。?/td> 650K
代理商： SLB128B
AC Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
LLHT
LHLT
TBIT
Parameter
Min
Typ
0.14
0.11
Max
0.8
0.8
Units
ns
ns
ns
LVDS Low-to-High Transition Time (
Figure 3
). (Note 7)
LVDS High-to-Low Transition Time (
Figure 3
). (Note 7)
Transmitter Output Bit Width
DUAL pin = V
CC
or
Gnd
DUAL pin =
1
2
V
CC
1/7 TCIP
2/7 TCIP
100
ns
ps
ns
TCCS
TPPOS0
TxOUT Channel to Channel Skew
Transmitter Output Pulse Position for Bit 0
(previous cycle) from CLK1P rising edge
(Note 7).
Transmitter Output Pulse Position for Bit1
(previous cycle) from CLK1P rising edge.
(Note 7)
Transmitter Output Pulse Position for Bit2
from CLK1P rising edge. (Note 7)
Transmitter Output Pulse Position for Bit3
from CLK1P rising edge. (Note 7)
Transmitter Output Pulse Position for Bit4
from CLK1P rising edge. (Note 7)
Transmitter Output Pulse Position for Bit5
from CLK1P rising edge. (Note 7)
Transmitter Output Pulse Position for Bit6
from CLK1P rising edge. (Note 7)
DxIN Setup to CLKINP (
Figure 6
) (Note 7)
DxIN Hold to CLKINP (
Figure 6
) (Note 7)
Transmitter Jitter Cycle-to-cycle (Note 4)
f = 65 MHz, DUAL pin
= V
CC
0.49
0
+0.49
TPPOS1
f = 65 MHz, DUAL pin
= V
CC
(1/7)TCIP
0.49
(1/7)TCIP
(1/7)TCIP
+0.49
ns
TPPOS2
f = 65 MHz, DUAL pin
= V
CC
f = 65 MHz, DUAL pin
= V
CC
f = 65 MHz, DUAL pin
= V
CC
f = 65 MHz, DUAL pin
= V
CC
f = 65 MHz, DUAL pin
= V
CC
(2/7)TCIP
0.49
(3/7)TCIP
0.49
(4/7)TCIP
0.49
(5/7)TCIP
0.49
(6/7)TCIP
0.49
0.8
0.8
(2/7)TCIP
(2/7)TCIP
+0.49
(3/7)TCIP
+0.49
(4/7)TCIP
+0.49
(5/7)TCIP
+0.49
(6/7)TCIP
+0.49
ns
TPPOS3
(3/7)TCIP
ns
TPPOS4
(4/7)TCIP
ns
TPPOS5
(5/7)TCIP
ns
TPPOS6
(6/7)TCIP
ns
TSTC
THTC
TJCC
ns
ns
ps
f = 85 MHz, DUAL pin
= Gnd
f = 54 MHz, DUAL pin
= V
CC
114
114
ps
TPLLS
TPDD
Transmitter Phase Lock Loop Set (
Figure 7
) (Note 7)
Transmitter Powerdown Delay (
Figure 8
) (Note 7)
Transmitter Input to Output Latency for
single in-to-dual out mode.
Figure 9
10
100
ms
ns
ns
f = 170 MHz (Note 6)
1.5 TCIP
+4.1
D
www.national.com
6
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