參數(shù)資料
型號： SPL505YC264BTT
廠商： Silicon Laboratories Inc
文件頁數(shù)： 21/27頁
文件大小： 0K
描述： IC CLOCK CK505 BEARLAKE 64TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU，PCI Express（PCIe）
輸入： 晶體
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:22
差分 - 輸入:輸出： 無/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SPL505YC26
......................Document #: 001-03543 Rev *E Page 3 of 27
31
SRC9#
O, DIF 100 MHz Differential serial reference clocks.
32
SRC11#/OE#_9
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
Default SRC11.
33
SRC11/OE#_10
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#10 Input controlling
SRC10. Default SRC11.
34
SRC10
O, DIF 100 MHz Differential serial reference clocks.
35
SRC#10
O, DIF 100 MHz Differential serial reference clocks.
36
VDD_SRC_IO
PWR
0.7V Power supply for SRC outputs.
37
SRC5#CPU_STOP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs/100 MHz Differential serial
reference clocks.
38
SRC5/PCI_STOP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs/100 MHz Differential
serial reference clocks.
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
40
SRC6#
O, DIF 100 MHz Differential serial reference clocks.
41
SRC6
O, DIF 100 MHz Differential serial reference clocks.
42
VSS_SRC
GND
Ground for outputs.
43
SRC7#/OE#_6
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#6 Input controlling
SRC6. Default SRC7.
44
SRC7/OE#_8
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8. Default SRC7.
45
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
46
SRC8#/CPUC2_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
47
SRC8/CPUT2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
48
IO_VOUT
O
Integrated Linear Regulator Control.
49
VDD_CPU_IO
PWR
0.7V Power supply for CPU outputs.
50
CPU1#
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode
depending on the configuration set in Byte 11 Bit3:2.
51
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode
depending on the configuration set in Byte 11 Bit3:2.
52
VSS_CPU
GND
Ground for outputs.
53
CPU#0
O, DIF Differential CPU clock outputs.
54
CPU0
O, DIF Differential CPU clock outputs.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
57
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
58
VSS_REF
GND
Ground for outputs.
Pin Definitions (continued)
Pin No.
Name
Type
Description
相關(guān)PDF資料
PDF描述
D38999/26JE26JA CONN PLUG 26POS STRAIGHT W/SCKT
V24B28H250B3 CONVERTER MOD DC/DC 28V 250W
ICS932S200BFLFT IC FREQ TIMING GENERATOR 56-SSOP
MS27473E24B4S CONN PLUG 56POS STRAIGHT W/SCKT
V24B24H250BG2 CONVERTER MOD DC/DC 24V 250W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SPL5100PT 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER
SPL520LLPT 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER
SPL53-1024 制造商:Power-One 功能描述:
SPL53-4000 制造商:Power-One 功能描述:
SPL-53-DR-IR1-CDA 制造商:SOURCE 制造商全稱:Source Photonics, Inc. 功能描述:SFP Bi-Directional Transceiver Preliminary
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*