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參數(shù)資料
| 型號： | SPL505YC264BTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK505 BEARLAKE 64TSSOP |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，PCI Express（PCIe） |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:22 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
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SPL505YC26
......................Document #: 001-03543 Rev *E Page 5 of 27
Frequency Select Pin (FSA, FSB, and FSC)
To achieve host clock frequency selection, apply the appro-
priate logic levels to FS_A, FS_B, and FS_C, inputs before
CK_PWRGD assertion (as seen by the clock synthesizer).
When CK_PWRGD is sampled HIGH by the clock chip
(indicating processor CK_PWRGD voltage is stable), the clock
chip samples the FS_A, FS_B, and FS_C, input values. For all
logic levels of FS_A, FS_B, and FS_C CK_PWRGDemploys
a one-shot functionality, in that once a valid HIGH on
CK_PWRGD has been sampled, all further CK_PWRGD
FS_A, FS_B, and FS_C, transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
.
Frequency Select Pin (FSA, FSB, and FSC)
Input Conditions
Output Frequency
FSC
FSB
FSA
CPU
(MHz)
SRC
(MHz)
SATA
(MHz)
DOT96
(MHz)
USB
(MHz)
PCI
(MHz)
REF
(MHz)
FSEL_2
FSEL_1
FSEL_0
1
0
1
100
96
48
33.3
14.318
0
1
133
0
1
166
0
1
0
200
0
266
1
0
333
1
0
400
1
200
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
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