- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9603 > SPL505YC264BTT (Silicon Laboratories Inc)IC CLOCK CK505 BEARLAKE 64TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | SPL505YC264BTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK505 BEARLAKE 64TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，PCI Express（PCIe） |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:22 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
SPL505YC26
....................Document #: 001-03543 Rev *E Page 15 of 27
PD# Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300
s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function. When the
CPU_STP# pin is asserted, all CPU outputs that are set with
the SMBus configuration to be stoppable via assertion of
CPU_STP# are stopped within two to six CPU clock periods
after being sampled by two rising edges of the internal CPUC
clock. The final states of the stopped CPU signals are CPUT
= HIGH and CPUC = LOW.
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 3. PD Assertion Timing Waveform
DOT96C
PD#
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8ms
PCI, 33MHz
REF
Tdrive_PW RDN#
<300
S, >200mV
PD Deassertion Timing Waveform
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| D38999/26JE26JA | CONN PLUG 26POS STRAIGHT W/SCKT |
| V24B28H250B3 | CONVERTER MOD DC/DC 28V 250W |
| ICS932S200BFLFT | IC FREQ TIMING GENERATOR 56-SSOP |
| MS27473E24B4S | CONN PLUG 56POS STRAIGHT W/SCKT |
| V24B24H250BG2 | CONVERTER MOD DC/DC 24V 250W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPL5100PT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SPL520LLPT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SPL53-1024 | 制造商:Power-One 功能描述: |
| SPL53-4000 | 制造商:Power-One 功能描述: |
| SPL-53-DR-IR1-CDA | 制造商:SOURCE 制造商全稱:Source Photonics, Inc. 功能描述:SFP Bi-Directional Transceiver Preliminary |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。