參數(shù)資料
型號: ST6375B1/XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝: SHRINK, PLASTIC, DIP-42
文件頁數(shù): 26/84頁
文件大?。?/td> 861K
代理商: ST6375B1/XXX
32/84
ST6365, ST6375, ST6385 ST6367, ST6377, ST6387
TIMERS (Cont’d)
4.2.1 Timer Operating Modes
Since in the ST638x devices the external TIMER
pin is not connected, the only allowed operating
mode is the output mode, which is selected by set-
ting bit 4 and by clearing bit 5 in the TSCR1 regis-
ter. This procedure will enable Timer 1 and
Timer 2.
Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On
this mode the timer prescaler is clocked by the
prescaler clock input (OSC/12). The user can se-
lect the desired prescaler division ratio through the
PS2/PS1/PS0 bits. When TCR count reaches 0, it
sets the TMZ bit in the TSCR.
The TMZ bit can be tested under program control
to perform timer functions whenever it goes high.
Bits D4 and D5 on TSCR2 (Timer 2) register are
not implemented.
Timer Interrupt
When the counter register decrements to zero and
the software controlled ETI (enable timer interrupt)
bit is set to one then an interrupt request associat-
ed to interrupt vector #3 (for Timer 1), to interrupt
vector #1 (for Timer 2) is generated. When the
counter decrements to zero also the TMZ bit in the
TSCR register is set to one.
Notes:
TMZ is set when the counter reaches 00h; howev-
er, it may be set by writing 00h in the TCR register
or setting the bit 7 of the TSCR register. TMZ bit
must be cleared by user software when servicing
the timer interrupt to avoid undesired interrupts
when leaving the interrupt service routine. After re-
set, the 8-bit counter register is loaded to FFh
while the 7-bit prescaler is loaded to 7Fh, and the
TSCR register is cleared which means that timer is
stopped (PSI=0) and timer interrupt disabled.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
Figure 21. Timer Working Principle
BIT0
BIT1
BIT2
BIT3
BIT6
BIT5
BIT4
CLOCK
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
1
02
3
4
5
67
PS0
PS1
PS2
VA00186
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