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參數(shù)資料
| 型號： | ST63T69B1 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機的數(shù)控多FREQUENCYMONITOR |
| 文件頁數(shù)： | 21/71頁 |
| 文件大?。?/td> | 584K |
| 代理商： | ST63T69B1 |
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Interrupt Procedure
The interruptprocedureis verysimilar to a call pro-
cedure; the user can consider the interrupt as an
asynchronous call procedure. As this is an asyn-
chronous event the user does not know about the
context and the time at which itoccurred. As a re-
sult the user should save all the data space regis-
ters whichwill be usedinsidetheinterrupt routines.
There are separate sets of processorflags for nor-
mal, interrupt and non-maskable interrupt modes
which are automaticallyswitched and so these do
not need to be saved.
The following list summarizes the interrupt proce-
dure (refer also to Figure 19. InterruptProcessing
Flow Chart):
-
Interrupt detection
-
The flags C and Z of the main routine are ex-
changed with the flags C and Z of the interrupt
routine (resp.the NMIflags)
-
The valueof the PC is stored in the first level of
the stack - The normal interrupt lines are inhib-
ited (NMIstill active)
-
The edgeflip-flop is reset
-
The relatedinterrupt vector is loaded in the PC.
-
User selected registers are saved inside the in-
terrupt service routine (normally on a software
stack)
-
The source of the interrupt is found by polling
(if more than one source is associated to the
same vector)
-
Interrupt servicing
-
Return frominterrupt (RETI)
-
Automatically the ST63xx core switches back
to the normal flags (resp the interrupt flags)
and pops the previous PC value fromthe stack
The interruptroutine begins usually by the identifi-
cation of the device that has generated the inter-
rupt request. The user should save the registers
which are used inside the interrupt routine (that
holds relevantdata) intoa software stack.
After the RETIinstruction execution,the Core car-
ries out the previous actions and the main routine
can continue.
ST6369 Interrupt Details
IR Interrupt (#0).
The IRIN/PC6 Interrupt is con-
nected to the first interrupt #0 (NMI, 0FFCH). Ifthe
IRINT interrupt is disabled at the Latch circuitry,
then itwill be high. The #0 interrupt input detectsa
high to low level. Note that once #0 has been
latched,
then
the only way to remove the
latched #0 signal is to service the interrupt. #0
can interrupt the other interrupts. A simple latch
is provided from the PC6(IRIN) pin in order to
generate the IRINT signal. This latch can be trig-
gered by either the positive or negative edge of
IRIN signal. IRINT is inverted with respect to the
latch. The latch can be read by software and re-
set bysoftware.
INTERRUPT
(Continued)
LOAD PC FROM
INTERRUPT VECTOR
( FFC / FFD )
SET
INTERRUPT MASK
PUSH THE
PC INTO THE STACK
SELECT
INTERNAL MODE FLAG
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
INSTRUCTION
WAS
THE INSTRUCTION
A RETI
IS THE CORE
ALREADY IN
NORMAL MODE
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
CLEAR
INTERRUPT MASK
SELECT
PROGRAM FLAGS
” POP ”
THE STACKED PC
NO
NO
YES
YES
NO
YES
VA000014
Figure 19. InterruptProcessingFlow-Chart
ST6369
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