參數(shù)資料
型號(hào)： ST63T69B1
廠商： 意法半導(dǎo)體
英文描述： 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR
中文描述： 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR
文件頁(yè)數(shù)： 22/71頁(yè)
文件大?。?/td> 584K
代理商： ST63T69B1
INTERRUPT
(Continued)
TIMER 2 Interrupt (#1).
The TIMER 2 Interrupt is
connectedtotheinterrupt#1(0FF6H). The TIMER 2
interrupt generatesa low level (which is latchedin
thetimer). Onlythelow levelselection for#1 canbe
used.Bit 6oftheinterrupt optionregister C8H hasto
beset.
VSYNC Interrupt (#2).
The VSYNC Interrupt is
connected to the interrupt #2. When disabled the
VSYNC INT signal is low. The VSYNC INT signal
is invertedwith respect to the signal applied to the
VSYNC pin. Bit 5 of the interrupt option register
C8H is used to select the negative edge (ES2=0)
or the positive edge (ES2=1); the edge will de-
pend on the application. Note thatonce an edge
has been latched, then the only way to remove
the latched signal is to service the interrupt. Care
must be taken not to generate spurious inter-
rupts. This interrupt may be used for synchronize
to the VSYNCsignal inordertochange characters
in the OSD only when the screen is on vertical
blanking (if desired). This method may also be
used toblink characters.
TIMER 1 Interrupt (#3).
The TIMER 1 Interruptis
connected to the fourthinterrupt#3 (0FF2H)which
detectsa low level(latched in the timer).
PWR Interrupt (#4).
The PWR Interrupt is con-
nected to the fifth interrupt #4 (0FF0H). If the
PWRINT is disabled at the PWR circuitry, then it
will be high. The #4 interrupt input detects a low
level. A simple latch is provided from the PC4
(PWRIN)pin in orderto generatethe PWRINT sig-
nal. This latch can be triggered by either the posi-
tive or negative edge of the
PWRINT is inverted with respect to the latch. The
latch can be resetby software.
Notes
Global disable does not reset edge sensi-
tive interruptflags. Theseedge sensitive interrupts
becomependingagainwhenglobaldisablingis re-
leased. Moreover, edge sensitive interrupts are
stored in therelated flags also when interrupts are
globallydisabled,unlesseachedge sensitiveinter-
rupt is also individually disabled before the inter-
rupting event happens. Global disable is done by
clearing the GEN bit of Interrupt option register,
while any individual disable is done in the control
register of the peripheral. The on-chip Timer pe-
ripheralshavean interruptrequestflagbit(TMZ),this
bitis settoonewhenthedevicewantstogeneratean
interruptrequestandamaskbit(ETI)thatmustbeset
toonetoallowthetransferofthe flagbittotheCore.
PWRIN
signal.
ST6369
18/67
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