參數(shù)資料
型號(hào)： ST63T69B1
廠商： 意法半導(dǎo)體
英文描述： 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR
中文描述： 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR
文件頁(yè)數(shù)： 8/71頁(yè)
文件大小： 584K
代理商： ST63T69B1
PIN DESCRIPTION
V
DD
andV
SS
.
Power is supplied to the MCU using
these twopins. V
DD
ispower andV
SS
istheground
connection.
OSCIN, OSCOUT.
These pins are internally con-
nected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the cor-
rect operation of the MCU with various stabil-
ity/cost trade-offs. The OSCIN pin is the input pin,
the OSCOUT pinis the outputpin.
RESET.
The active low RESET pin is used to start
the microcontroller to thebeginning of its program.
Additionally the quartz crystal oscillator will be dis-
abled when theRESETpin is low to reducepower
consumption duringreset phase.
TEST.
The TEST pin must be held at V
SS
for nor-
mal operation.
PA0-PA7.
These 8 linesare organized as one I/O
port (A). Each line may be configured as either an
input withor withoutpull-upresistoror asan output
under software control of the data direction regis-
ter. PinsPA4 to PA7 are configured asopen-drain
outputs (12V drive). On PA4-PA7 pins the input
pull-up option is not available while PA6 and PA7
have additional current driving capability (25mA,
V
OL
:1V). PA0 to PA3 pins are configured as push-
pull.
PB1-PB2, PB4-PB6.
These 5 lines are organized
as oneI/Oport(B).Each linemay be configuredas
either aninput withorwithoutinternalpull-up resis-
tor or as an output under software control of the
data directionregister.
PC0-PC7.
These 8 lines are organized as one I/O
port (C). Each line maybe configured as either an
input with or without internal pull-up resistoror as
an output under softwarecontrol of thedata direc-
tion register. Pins PC0 to PC3 are configured as
open-drain(5V drive) in output mode while PC4 to
PC7 are open-drain with 12V drive and the input
pull-up options does not exist on these four pins.
PC0, PC1and PC3lines when in output mode are
“ANDed” with the SPI control signals and are all
open-drain.PC0is connected to theSPI clock sig-
nal (SCL), PC1 with the SPI data signal (SDA)
while PC3 is connected with SPI enable signal
(SEN, usedin S-BUSprotocol). Pin PC4 and PC6
can alsobe inputsto softwareprogrammableedge
sensitive latches which can generate interrupts;
PC4 can be connected to Power Interrupt while
PC6 can be connected to the HSYNC/NMI inter-
rupt line.
DA0-DA5.
These pins are the six PWM D/A out-
puts of the 6-bit on-chip D/A converters. These
lines have open-drain outputs with 12V drive. The
output repetition rate is 31.25KHz (with 8MHz
clock).
AD.
This is the input of the on-chip 10 levels com-
parator that can be used to implement the Analog
Keyboard function. This pin is an high impedance
input able to withstand signals with a peak ampli-
tude up to 12V.
VSYNC.
This is the Vertical Synchronization pin.
This pinis connected to an internal timer interrupt.
O0,O1.
Thesetwolinesareoutputopen-drain pins
with 12Vdrive.
HDA.
This is the output pin of the on-chip 14-bit
PWMD/A Converter.This lineis apush-pulloutput
with standarddrive.
ST6369
4/67
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