參數(shù)資料
型號(hào)： ST63T69B1
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR
中文描述： 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR
文件頁(yè)數(shù)： 46/71頁(yè)
文件大?。?/td> 584K
代理商： ST63T69B1
DLCR
DedicatedLatches Control
Register
(E9H, WriteOnly)
D7 D6 D5 D4 D3 D2 D1 D0
Unused
HSYEDGE
HSYINTEN
RESHSYLAT
PWREDGE
PWRINTEN
RESPWRLAT
Unused
Figure 55. DedicatedLatches Control Register
DEDICATED LATCHES
Two latchesare available which may generatein-
terrupts to the ST6369 core.
The HSYNC latch is set either by thefalling or ris-
ing edge ofthe signal on pin PC6(HSYNC). If bit 1
(HSYEDGE) of the latches register (E9H) is high,
then thelatch will betriggered on the rising edge of
the signal at PC6(HSYNC). Ifbit 1 (HSYEDGE)is
low, then the latch will be triggered on the falling
edge of the signal at PC6(HSYNC). The HSYNC
latch can be reset by settingbit3 (RESHSYLAT)of
the latches register; the bit is set only and a high
should be written every time the HSYNC latch
needs to be reset. If bit 2 (HSYINTEN) of the
latches register (E9H) is high, then the output of
the HSYNC latch, HSYNCN, may generate an in-
terrupt (#0). HSYNCN is inverted with respect to
the stateof the HSYNC latch. If bit 2 (HSYINTEN)
is low, then the output of the HSYNC latch,
HSYNCN, is forced high. The state of the HSYNC
latch may be read from bit 3 (HSYNC) of register
E4H; if the HSYNC latch is set, then bit 3 will be
high.
The PWR latch is set either by the falling or rising
edge of the signal on pin PC4(PWRIN). If bit 4
(PWREDGE) of the latches register(E9H) is high,
then thelatch will betriggered on the rising edge of
the signal at PC4(PWRIN). If bit 4 (PWREDGE) is
low, then the latch will be triggered on the falling
edge ofthe signal at PC4(PWRIN). The PWR latch
can be reset by setting bit6 (RESPWRLAT) of the
latches register; the bit is set only and a high
should be written everytime thePWR latch needs
to bereset. Ifbit5 (PWRINTEN) of thelatches reg-
ister (E9H) is high, then the output of the PWR
latch, PWRINTN, may generate an interrupt (#4).
PWRINTN is inverted with respect to the state of
the PWR latch. If bit 5 (PWRINTEN) is low, then
the output of the PWR latch, PWRINTN, is forced
high.
D0.
This bitis not used
D7
. This bit is not used
RESPWRLAT.
ResetsthePWRlatch;thisbitisset
only.
PWRINTEN.
Thisbit enablesthe PWRINTNsignal
(#4) fromthe latch to the ST6369 core. Undefined
after reset.
PWREDGE.
The bit determines the edge which
will cause the PWRIN latch to be set. If this bit is
high, thanthe PWRIN latch will be set on therising
edge of the PWRIN signal. Undefined after reset.
RESHSYLAT.
Resets the HSYNC latch; this bit is
set only.
HSYINTEN.
This bit enables the HSYNCN signal
(#0) fromthe latch to the ST6369 core. Undefined
after reset.
HSYEDGE.
The bitdeterminesthe edge whichwill
cause the HSYNC latch to be set. If thisbit is high,
than theHSYNClatch willbe setonthe rising edge
of the HSYNC signal.Undefinedafter reset.
ST6369
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