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參數(shù)資料
| 型號： | ST63T69B1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機的數(shù)控多FREQUENCYMONITOR |
| 文件頁數(shù)： | 44/71頁 |
| 文件大?。?/td> | 584K |
| 代理商： | ST63T69B1 |
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6-BIT PWMD/A CONVERTERS
The D/A macrocell contains up to six PWM D/A
outputs (31.25kHzrepetition,DA0-DA5)with six bit
resolution.
Each D/Aconverterof ST6369is composed bythe
following main blocks:
- pre-divider
- 6-bitcounter
- data latches and compare circuits
The pre-divider uses the clock input frequency
(8MHz typical) and its output clocks the 6-bit free-
running counter. The data latched in thesix regis-
ters (E0H, E1H, E2H, E3H, E6H and E7H)control
the six D/Aoutputs (DA0,1,2,3, 4 and 5). When all
zeros are loaded the relevant output is an high
logic level;all 1’s correspond to apulse with a1/64
duty cycle and almost 100%zero level.
The repetition frequency is 31.25KHz and is re-
lated to the 8MHz clock frequency.Use of a differ-
ent oscillator frequency will result in a different
repetition frequency. All D/A outputs are open-
drain with standard current drive capability and
able towithstandup to 12V.
Figure50. DA0-DA5 Data/Control Registers
DA0-DA5.
These are the 6 bits of the PWMdigital
to analog converter.Undefined afterreset.
A/D COMPARATOR
A/D INPUT,HSYNC/PC6 RESULT,
VSYNC RESULT AND O0, O1OUTPUTS
The A/D macrocell contains an A/D comparator
with fivelevelsatintervalsof 1V from1V to5V. The
levels canall belowered by0.5Vto effectivelydou-
ble theresolution.
The A/D used to perform the AFC function (when
high threshold is selected) has the following volt-
age levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result
register (E4H address) will provide the result in bi-
nary form (less than 1V is 000, greater than 5V is
101).
If the application requires a greater resolution, the
sensitivity can be doubled by clearing to zero bit 2
of the OUTPUTS control register,address E5H. In
this case all levelsare shifted lower by 0.5V.If the
two results are now added within a software rou-
tine then the A/D S-curve can be located within a
resolution of 0.5V.
The A/D input has high impedance able to with-
stand up to 13V signals (input level tolerances
±
200mVabsolute and
±
100mvrelative to 5V).
DA0, DA1, DA2, DA3, DA4, DA5
DA0 toDA5 Data/control Registers
(E0H, E1H, E2H, E3H,E6H, E7H Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit0
Data Bit1
Data Bit2
Data Bit3
Data Bit4
Data Bit5
Unused
Unused
Figure51.6-bit PWM D/A Output Configuration
Figure 52. A/D Inputs Configuration Diagram
ST6369
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