參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 150/178頁
文件大?。?/td> 1097K
代理商： ST92E141K4D1
73/178
ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.5 OSCILLATOR CHARACTERISTICS
The on-chip oscillator circuit uses an inverting gate
circuit with tri-state output.
Notes:
Owing to the Q factor required, Ceramic
Resonators may not provide a reliable oscillator
source.
OSCOUT must not be directly used to drive exter-
nal circuits.
When the oscillator is stopped, OSCOUT goes
high impedance.
The parallel resistor, R, is disconnected and the
oscillator is disabled, forcing the internal clock,
CLOCK1, to a high level, and OSCOUT to a high
impedance state.
To exit the HALT condition and restart the oscilla-
tor, an external RESET pulse is required.
It should be noted that, if the Watchdog function is
enabled, a HALT instruction will not disable the os-
cillator. This to avoid stopping the Watchdog if a
HALT
code is executed in error. When this occurs,
the CPU will be reset when the Watchdog times
out or when an external reset is applied.
Figure 34. Crystal Oscillator
Table 17. Crystal Specification (5V)
Legend:
CL1,CL2: Maximum Total Capacitances on pins OSCIN
and OSCOUT (the value includes the external capaci-
tance tied to the pin CL1 and CL2 plus the parasitic capac-
itance of the board and of the device).
Note: The tables are relative to the fundamental quartz
crystal only (not ceramic resonator).
Figure 35. Internal Oscillator Schematic
Figure 36. External Clock
OSCIN
OSCOUT
CL1
CL2
ST9
CRYSTAL CLOCK
VR02116A
1M*
*Recommended for oscillator stability
Rs max
(ohm)
CL1=CL2=
56pF
CL1=CL2=
47pF
CL1=CL2=
22pF
Freq.=
3 MHz
270
350
850
Freq.=
4 MHz
150
200
510
Freq.=
5 MHz
110
120
340
VR02086A
HALT
OSCIN
OSCOUT
RIN
ROUT
R
OSCIN
OSCOUT
CLOCK
INPUT
NC
EXTERNAL CLOCK
VR02116B
ST9
1
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