參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 9/178頁
文件大?。?/td> 1097K
代理商： ST92E141K4D1
106/178
ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.4 Interrupt Management
The interrupts of the Extended Function Timer are
mapped on the eight external interrupt channels of
the microcontroller (refer to the “Interrupts” chap-
ter).
Depending on device specification, one of the fol-
lowing configurations can occur:
– The three interrupt sources are mapped on three
different interrupt channels (to use this feature,
the EFTIS bit must be reset)
– The three interrupt sources are mapped on the
same interrupt channel (to use this feature, the
EFTIS bit must be set)
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
Page 0)
– A pending bit in the EIPR register (R243 -
Page 0)
– A mask bit in the EIMR register (R244 - Page 0)
Program the interrupt priority level using the
EIPLR register (R245 - Page 0). For a description
of these registers refer to the “Interrupts” and
“DMA” chapters.
Use of three interrupt channels
To use the interrupt features, for each interrupt
channel used, perform the following sequence:
– Set the priority level of the interrupt channel(s)
used for the Extended Function Timer (EIPRL
register)
– Select the interrupt trigger edge(s) as rising edge
(set the corresponding bit(s) in the EITR register)
– Set the OCIS and/or ICIS and/or TOIS bit(s) of
the CR3 register to select the peripheral interrupt
source(s)
– Set the OCIE and/or ICIE and/or TOIE bit(s) of
the CR1 register to enable the peripheral to per-
form interrupt requests on the desiderate events
– In the EIPR register, reset the pending bit(s) of
the interrupt channels used by the peripheral in-
terrupts to avoid any spurious interrupt requests
being performed when the mask bit(s) is/are set
– Set the mask bit(s) of the interrupt channel(s)
used to enable the MCU to acknowledge the in-
terrupt requests of the peripheral.
Use of one external interrupt channel for all the
interrupts
To use the interrupt features, perform the following
sequence:
– Set the priority level of the interrupt channel used
(EIPRL register)
– Select the interrupt trigger edge as rising edge
(set the corresponding bit in the EITR register)
– Set the EFTIS bit of the CR3 register to select
the peripheral interrupt sources
– Set the OCIE and/or ICIE and/or TOIE bit(s) of
the CR1 register to enable the peripheral to per-
form interrupt requests on the wanted events
– In the EIPR register, reset the pending bit of the
interrupt channel used by the peripheral inter-
rupts to avoid any spurious interrupt requests be-
ing performed when the mask bits is set
– Set the mask bits of the interrupt channels used
to enable the MCU to acknowledge the interrupt
requests of the peripheral.
Caution: Care should be taken when using only
one of the input capture pins, as both capture in-
terrupts are enabled by the ICIE bit in the CR1 reg-
ister. If only ICAP1 is used (for example), an inter-
rupt can still be generated by the ICAP2 pin when
this pin toggles, even if it is configured as a stand-
ard output. If this case, the interrupt capture status
bits in the SR register should handled in polling
mode.
Caution:
1. It is mandatory to clear all EFT interrupt flags
simultaneously at least once before exiting an
EFT timer interrupt routine (the SR register
must = 00h at some point during the interrupt
routine), otherwise no interrupts can be issued
on that channel anymore.
Refer to the following assembly code for an
interrupt sequence example.
2. Since a loop statement is needed inside the IT
routine, the user must avoid situations where
an interrupt event period is narrower than the
duration of the interrupt treatment. Otherwise
nested interrupt mode must be used to serve
higher priority requests.
9
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