參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 17/178頁
文件大小： 1097K
代理商： ST92E141K4D1
113/178
ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
STATUS REGISTER (SR)
R254 - Read Only
Register Page: 28
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 = ICF1
Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1
Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 5 = TOF
Timer Overflow.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2
Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
Bit 3 = OCF2
Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 2-0 = Reserved, forced by hardware to 0.
CONTROL REGISTER 3 (CR3)
R255 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
Bit 7-4 = Unused
Read as 0.
Bit 3 = TOIS
Timer Overflow Interrupt Selection.
0: Select External interrupt.
1: Select Timer Overflow Interrupt.
Bit 2 = OCIS
Output Compare Interrupt Selection.
0: Select External interrupt.
1: Select Timer Output Compare Interrupt.
Bit 1 = ICIS
Input Capture Interrupt Selection.
0: Select External interrupt.
1: Select Timer Input Capture Interrupt.
Bit 0 = EFTIS
Global Timer Interrupt Selection.
0: Select External interrupt.
1: Select Global Timer Interrupt.
70
ICF1
OCF1
TOF
ICF2
OCF2
0
70
0
TOIS
OCIS
ICIS
EFTIS
9
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