參數(shù)資料
型號： ST92E141K4D1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù)： 41/178頁
文件大小： 1097K
代理商： ST92E141K4D1
135/178
ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
7.5 SERIAL PERIPHERAL INTERFACE (SPI)
7.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another Microcontroller.
Refer to the Pin Description chapter for the device-
specific pin-out.
7.5.2 Main Features
s
Full duplex, three-wire synchronous transfers
s
Master or slave operation
s
Four master mode frequencies
s
Maximum slave mode frequency = INTCLK/2.
s
Fully programmable 3-bit prescaler for a wide
range of baud rates, plus a programmable
divider by 2
s
Programmable clock polarity and phase
s
End of transfer interrupt flag
s
Write collision flag protection
s
Master mode fault protection capability.
7.5.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
To use any of these alternate functions (input or
output), the corresponding I/O port must be pro-
grammed as alternate function output.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 71.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 74) but master and slave
must be programmed with the same timing mode.
Figure 71. Serial Peripheral Interface Master/Slave
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
SCK
SLAVE
MASTER
SS
+5V
MSBit
LSBit
MSBit
LSBit
9
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