參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 103/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
103
Lucent Technologies Inc.
Timing Characteristics
Microprocessor Interface Timing
The I/O timing specifications for the microprocessor interface are given in Table 118 and shown in Figures 25—32.
The microprocessor interface pins use CMOS I/O levels. All outputs, except the address/data bus AD[7:0], are
rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write
cycle time is 200 ns for all device configurations.
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 25—32.
Table 118. Microprocessor Interface I/O Timing Specifications
Symbol
Configuration
Parameter
Setup
(ns)
(Min)
—
10
—
10
5
30
—
—
—
—
—
—
—
—
5
10
—
5
—
—
10
—
Hold
(ns)
(Min)
10
—
10
—
—
—
—
—
—
15
5
—
—
5
—
—
5
—
10
—
—
10
Delay
(ns)
(Max)
—
—
—
—
—
—
25
20
50
—
—
20
10
—
—
—
—
—
—
20
—
—
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
Modes 1 & 2
AS Asserted Width
Address Valid to AS Asserted (deMUX)
AS Asserted to Address Invalid (deMUX)
CS Asserted to AS Asserted
R/W Valid to DS Asserted (read)
AS Asserted to DS Asserted
CS Asserted to DTACK High
DS Asserted to DTACK Asserted (read)
DS Asserted to Data Valid
DS Deasserted to CS Deasserted
DS Deasserted to R/W Invalid
DS Deasserted to DTACK Deasserted
CS Deasserted to DTACK High Impedance
DS Deasserted to Data Invalid (read)
R/W Valid to DS Asserted (write)
AS Asserted to DS Asserted (write)
DS Asserted Width (write)
Data Valid to DS Asserted (write)
DS Deasserted to Data Invalid (write)
DS Asserted to DTACK Asserted (write)
Address Valid to AS Asserted (MUX)
AS Asserted to Address Invalid (MUX)
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