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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 13/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
13
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
*
I
u
indicates an internal pull-up; I
d
indicates an internal pull-down.
Pin
Symbol
Type
*
Name/Description
21
MPMODE
I
Microprocessor Mode.
When MPMODE = 1, the device uses the address
latch enable type microprocessor read/write protocol with separate read and
write controls. Setting MPMODE = 0 allows the device to use the address
strobe type microprocessor read/write protocol with a separate data strobe
and a combined read/write control.
20
MPMUX
I
Microprocessor Multiplex Mode.
Setting MPMUX = 1 allows the
microprocessor interface to accept multiplexed address and data signals.
Setting MPMUX = 0 allows the microprocessor interface to accept
demultiplexed (separate) address and data signals.
19
WR_DS
I
Write (Active-Low).
If MPMODE = 1 (pin 21), this pin is asserted low by the
microprocessor to initiate a write cycle.
Data Strobe (Active-Low).
If MPMODE = 0 (pin 21), this pin becomes the
data strobe for the microprocessor. When R/W = 0 (pin 22) initiating a write, a
low applied to this pin latches the signal on the data bus into internal
registers.
22
RD_R/W
I
Read (Active-Low).
If MPMOD = 1 (pin 21), this pin is asserted low by the
microprocessor to initiate a read cycle.
Read/Write.
If MPMODE = 0 (pin 21), this pin is asserted high by the
microprocessor to initiate a read cycle or asserted low to initiate a write cycle.
23
ALE_AS
I
Address Latch Enable.
If MPMODE = 1 (pin 21), this pin becomes the
address latch enable for the microprocessor. When this pin transitions from
high to low, the address bus inputs are latched into the internal registers.
Address Strobe (Active-Low).
If MPMODE = 0 (pin 21), this pin becomes
the address strobe for the microprocessor. When this pin transitions from
high to low, the address bus inputs are latched into the internal registers.
24
CS
I
u
Chip Select (Active-Low).
This pin is asserted low by the microprocessor to
enable the microprocessor interface. If MPMUX = 1 (pin 20),
CS
can be
externally tied low to use the internal chip selection function. An internal
100 k
pull-up is on this pin.
Interrupt.
This pin is asserted high to indicate an interrupt produced by an
alarm condition in register 0 or 1. The activation of this pin can be masked by
microprocessor registers 2, 3, and 4.
25
INT
O
26
RDY_DTACK
O
Ready.
If MPMODE = 1 (pin 21), this pin is asserted high to indicate the
device has completed a read or write operation. This pin is in a 3-state
condition when CS (pin 24) is high.
Data Transfer Acknowledge (Active-Low).
If MPMODE = 0 (pin 21), this
pin is asserted low to indicate the device has completed a read or write
operation.
11, 27,
41, 61,
78, 91
GND
D
P
Ground Reference for Microprocessor Interface and Digital Circuitry.
12, 28,
40, 62,
77, 90
V
DDD
P
Power Supply for Microprocessor Interface and Digital Circuitry.
The
T7698 device requires a 5 V ± 5% power supply on these pins.
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