參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 77/112頁(yè)
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
77
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Monitor Parameter/Control Registers
(continued)
Errored Second Threshold Register (Framer_PR8)
This 8-bit register defines the errored event threshold for an errored second (ES). A one-second interval with errors
less than the ES threshold value is not an errored second. Programming 00(hex) into this register disables the
errored second threshold monitor circuitry.
Table 58. Errored Second Threshold Register (Framer_PR8)
Severely Errored Second Threshold Register (Framer_PR9—Framer_PR10)
This 16-bit register defines the errored event threshold for a severely errored second (SES). A one-second interval
with errors less than the SES threshold value is not a severely errored second. Programming 00(hex) into these
two registers disables the severely errored second threshold monitor circuitry.
Table 59. SES Threshold Register (Framer_PR9—Framer_PR10)
Bursty Errored Second Threshold Register (Framer_PR11)
This 8-bit register defines the errored event threshold for a bursty errored second (BES). A one-second interval
with errors less than the BES threshold value is not a BES. Programming 00(hex) in this register disables the BES
threshold monitor circuitry.
Table 60. BES Threshold Register (Framer_PR11)
Frame Monitor Exercise Register (Framer_PR12)
This register is for simulation purposes only. Set register to 00(hex) during normal operation.
Table 61. Frame Monitor Exercise Register (Framer_PR12)
Register
Framer_PR8
Bits
7—0
Description
ES Threshold Register (bit 7—bit 0)
Register
Framer_PR9
Framer_PR10
Bits
7—0
7—0
Description
SES MSB Threshold Register (bit 15—bit 8)
SES LSB Threshold Register (bit 7—bit 0)
Register
Framer_PR11
Bits
7—0
Description
BES Threshold Register (bit 7—bit 0)
Bits
5—0
Description
See Table 62.
Second Pulse Interval
1 s Pulse
500 ms Pulse
100 ms Pulse
Manufacturer’s Test
6
0
0
1
1
7
0
1
0
1
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