參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 68/112頁(yè)
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
68
Lucent Technologies Inc.
Frame Monitors
(continued)
Alarms and Performance Monitoring
(continued)
6.
Failed state
alarm or the
unavailable state alarm
.
A. The default mode asserts this alarm upon detection of ten consecutive severely errored second events and
deasserts this alarm upon detection of ten consecutive seconds which were not severely errored. The
corresponding performance counters are incremented appropriately.
B. Optionally, the T7698 can be programmed according to ITU Rec. G.826 (by setting register Framer_PR2,
bit 4 high) to process the unavailable state at the onset of the unavailable state (at the beginning of the ten
consecutive severely errored interval), and inhibit the increment of the severely errored and errored second
counters for the duration of the unavailable state. In this mode, the contents of the performance counters
contain information delayed by ten seconds. Out of unavailable state is entered at the onset of ten
consecutive seconds that were not severely errored.
7.
The
4-bit Sa6 codes
(Sa6_
hex
) are asserted if three consecutive 4-bit patterns have been detected. The
alarms are disabled when three consecutive 4-bit Sa6 codes have been detected that are different from the
pattern previously detected. The receive frame monitors the Sa6 bits for special codes described in ETS Draft
prETS 300 233:1992, Section 9.2. The Sa6 codes are defined in Table 40 and Table 41. The Sa6 codes in
Table 40 can be recognized as an asynchronous bit stream in either non-CRC-4 or CRC-4 modes as long as
the receive frame monitor is in the basic frame alignment state. In the CRC-4 mode, the receive frame monitor
can be forced to recognize the received Sa6 codes in Table 40 synchronously to the CRC-4 submultiframe
structure as long as the receive frame monitor has achieved CRC-4 multiframe alignment (synchronous Sa6
monitoring can be enabled by setting bit 1 of register Framer_PR2 high).
Table 40. Sa6 Bit Coding Recognized by the T7698 Receive Frame Monitor
Code
First Receive Bit (MSB)
. . .
Last Received Bit (LSB)
Sa6_8
hex
1
0
0
0
Sa6_A
hex
1
0
1
0
Sa6_C
hex
1
1
0
0
Sa6_E
hex
1
1
1
0
Sa6_F
hex
1
1
1
1
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