參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 12/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
12
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
*
I
u
indicates an internal pull-up; I
d
indicates an internal pull-down.
Pin
Symbol
Type
*
Name/Description
13, 39,
63, 89
RND/BPV[4:1]
O
Receive Negative Data.
When in dual-rail (DUAL = 1: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), this signal is the received
negative NRZ data to the terminal equipment. When in data slicing mode
(CDR = 0), this signal is the raw sliced negative data of the front end. For
frame monitor operation, clock recovery mode (CDR = 1) must be chosen.
Bipolar Violation.
When in single-rail (DUAL = 0: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), and CODE = 1 (register 5, bit 3),
this signal is asserted high to indicate the occurrence of a code violation in
the receive data stream. A code violation is a bipolar violation that is not part
of a zero substitution code. If CODE = 0, this signal is asserted to indicate
the occurrence of a bipolar violation in the received data.
Receive Positive Data.
When in dual-rail (DUAL = 1: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), this signal is the received positive
NRZ data to the terminal equipment. When in data slicing mode (CDR = 0),
this signal is the raw sliced positive data of the front end. For frame monitor
operation, clock recovery mode (CDR = 1) must be chosen.
Receive Data.
When in single-rail (DUAL = 0: register 5, bit 4) clock recovery
mode (CDR = 1: register 5, bit 0), this signal is the received NRZ data.
Receive Clock.
In clock recovery mode (CDR = 1: register 5, bit 0), this
signal is the recovered receive clock for the terminal equipment. The duty
cycle of RCLK is 50% ± 5%.
Analog Loss of Signal.
In data slicing mode (CDR = 0: register 5, bit 0), this
signal is asserted high to indicate low amplitude receive data at the RTIP/
RRING inputs.
Transmit Negative Data.
This signal is the transmit negative NRZ data from
the terminal equipment.
Transmit Positive Data.
When in dual-rail mode (DUAL = 1: register 5, bit 4),
this signal is the transmit positive NRZ data from the terminal equipment.
Transmit Data.
When in single-rail mode (DUAL = 0: register 5, bit 4), this
signal is the transmit NRZ data from the terminal equipment.
Transmit Clock.
DS1 (1.544 MHz ± 32 ppm) or CEPT (2.048 MHz ±
50 ppm) clock signal from the terminal equipment.
14, 38,
64, 88
RPD/
RDATA[4:1]
O
15, 37,
65, 87
RCLK/
ALOS[4:1]
O
16, 36,
66, 86
17, 35,
67, 85
TND[4:1]
I
TPD/
TDATA[4:1]
I
18, 34,
68, 84
TCLK[4:1]
I
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