TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
List of Figures
1-1
TAS5508B Functional Structure
.................................................................................................
111-2
Typical TAS5508B Application (DVD Receiver)
..............................................................................
131-3
Pass-Through Output Mixer TAS5508B Channel Configuration
............................................................
132-1
TAS5508B DAP Architecture With I
2C Registers (f
S ≤ 96 kHz) .............................................................
2-2
TAS5508B Architecture With I
2C Registers (f
S = 176.4 kHz or fS = 192 kHz) ............................................
2-3
TAS5508B Detailed Channel Processing
......................................................................................
232-4
5.23 Format
........................................................................................................................
242-5
Conversion Weighting Factors—5.23 Format to Floating Point
.............................................................
242-6
Alignment of 5.23 Coefficient in 32-Bit I
2C Word
.............................................................................
242-7
25.23 Format
......................................................................................................................
252-8
Conversion Weighting Factors—25.23 Format to Floating Point
...........................................................
252-9
Alignment of 25.23 Coefficient in Two 32-Bit I
2C Words
.....................................................................
262-10
TAS5508B Digital Audio Processing
...........................................................................................
272-11
Input Crossbar Mixer
.............................................................................................................
272-12
Biquad Filter Structure
............................................................................................................
282-13
Automute Threshold
..............................................................................................................
302-14
Loudness Compensation Functional Block Diagram
.........................................................................
312-15
Loudness Example Plots
.........................................................................................................
322-16
DRC Positioning in TAS5508B Processing Flow
.............................................................................
332-17
Dynamic Range Compression (DRC) Transfer Function Structure
........................................................
342-18
Output Mixers
......................................................................................................................
382-19
De-Emphasis Filter Characteristics
.............................................................................................
392-20
Power-Supply and Digital Gains (Linear Space)
..............................................................................
402-21
Power-Supply and Digital Gains (Log Space)
.................................................................................
402-22
Block Diagrams of Typical Systems Requiring TAS5508B Automatic AM Interference-Avoidance Circuit
4-1
Slave Mode Serial Data Interface Timing
......................................................................................
544-2
Start and Stop Conditions Timing Waveforms
................................................................................
554-3
I
2C Pullup Circuit (With No Series Resistor)
...................................................................................
564-4
I
2C Pullup Circuit (With Series Resistor)
.......................................................................................
564-5
Reset Timing
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574-6
Power-Down Timing
..............................................................................................................
574-7
Error-Recovery Timing
...........................................................................................................
584-8
Mute Timing
........................................................................................................................
584-9
HP_SEL Timing
...................................................................................................................
594-10
I
2S 64-f
S Format ...................................................................................................................
4-11
Left-Justified 64-fS Format ....................................................................................................... 61 4-12
Right-Justified 64-fS Format ..................................................................................................... 62 5-1
Typical I
2C Sequence
.............................................................................................................
635-2
Single-Byte Write Transfer
.......................................................................................................
64List of Figures
5