5.2
Single- and Multiple-Byte Transfers
5.3
Single-Byte Write
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
T0036-01
TAS5508B
8-Channel Digital Audio PWM Processor
SLES162C – DECEMBER 2005 – REVISED JULY 2009
www.ti.com
The serial-control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data
processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write
operations.
During multiple-byte read operations, the TAS5508B responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a
particular subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the TAS5508B compares the number of bytes transmitted to the
number of bytes that are required for each specific subaddress. If a write command is received for a
biquad subaddress, the TAS5508B expects to receive five 32-bit words. If fewer than five 32-bit data
words have been received when a stop command (or another start command) is received, the data
received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5508B
expects to receive one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5508B also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS5508B. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written. As is true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data
is discarded.
As shown in
Figure 5-2, a single-byte, data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct
I2C device address and the read/write bit, the TAS5508B device responds with an acknowledge bit. Next,
the master transmits the address byte or bytes corresponding to the TAS5508B internal memory address
being accessed. After receiving the address byte, the TAS5508B again responds with an acknowledge bit.
Next, the master device transmits the data byte to be written to the memory address being accessed. After
receiving the data byte, the TAS5508B again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte, data-write transfer.
Figure 5-2. Single-Byte Write Transfer
64
I2C Serial-Control Interface (Slave Addresses 0x36 and 0x37)