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參數(shù)資料
| 型號(hào)： | TDA9109N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低費(fèi)用偏轉(zhuǎn)處理器多同步監(jiān)測(cè)儀 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 303K |
| 代理商： | TDA9109N |
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OPERATINGDESCRIPTION
I - GENERALCONSIDERATIONS
I.1 - Power Supply
The typical values of the power supply voltages
V
CC
and V
DD
are 12V and 5V respectively. Opti-
mum operation is obtained for V
CC
between 10.8
and 13.2V and V
DD
between4.5 and 5.5V.
Inordertoavoiderraticoperationofthecircuitduring
the transient phaseof V
CC
switchingon, or off, the
value of V
CC
is monitored : if V
CC
is less than
7.5Vtyp., theoutputsof the circuit areinhibited.
Similarly, before V
DD
reaches4V, all the I
2
C register
areresettotheirdefaultvalue(seeI
2
CControlTable).
In order to havevery good power supply rejection,
the circuit is internally suppliedby several voltage
references (typ. value : 8V).Two of these voltage
references are externally accessible, one for the
vertical and one for the horizontal part. They can
be used to bias external circuitry (if I
LOAD
is less
than5mA). Itis necessarytofilterthe voltagerefer-
encesby externalcapacitorsconnectedto ground,
inorderto minimizethenoiseandconsequentlythe
”jitter”on verticaland horizontaloutputsignals.
I.2 - I
2
C Control
TDA9109/N belongs to the I
2
C controlled device
family. Instead of being controlled by DC voltages
on dedicatedcontrolpins, each adjustmentcanbe
done via the I
2
C Interface.
The I
2
C bus is a serial bus with a clockand a data
input.Thegeneralfunctionandthebusprotocolare
specified in the Philips-bus data sheets.
Theinterface(DataandClock)isa comparatorwith
hysteresis;thethresholds(less then2.2V onrising
edge, more than 0.8V on falling edge with 5V
supply)are TTL-compatible. Spikes of up to 50ns
arefilteredby anintegratorandthemaximumclock
speedis limited to 400kHz.
The data line (SDA) can be used bidirectionally.
In read-mode the IC sends reply information
(1 byte) to themicro-processor.
The bus protocol prescribes a full-byte transmis-
sion in all cases. The first byte after the start
condition is used to transmit the IC-address
(hexa 8C for write, 8D for read).
I.3 - Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controlstoaffect)andthethirdbytethecorrespond-
ing databyte. It is possibleto sendmore than one
data byte to the IC.If afterthe thirdbyte no stop or
start condition is detected, the circuit increments
automaticallyby onethemomentarysubaddressin
the subaddress counter (auto-increment mode).
So it ispossible totransmitimmediatelythe follow-
ing data bytes without sending the IC address or
subaddress.This canbeusefulto reinitializeallthe
controls very quickly (flash manner). This proce-
dure can be finished by a stop condition.
The circuithas 14adjustmentcapabilities:1 forthe
horizontal part, 4 for the vertical, 2 for the E/W
correction,2 forthedynamichorizontalphasecon-
trol,1 for the Moiré option, 3 for the horizontal and
the vertical dynamic focus and 1 for the B+ refer-
ence adjustment.
17 bits are also dedicated to several controls
(ON/OFF, Horizontal Forced Frequency,Sync Pri-
ority, DetectionRefresh and XRAYreset).
I.4 - Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the horizontal and vertical
lock/unlockstatus,the XRAYactivationstatusand,
the horizontalandverticalpolaritydetection.It also
containsthesyncdetectionstatuswhichisusedby
the MCU toassign the sync priority.
Astopconditionalwaysstopsalltheactivitiesofthe
bus decoderand switchesto high impedanceboth
the data and clock line (SDAand SCL).
See I
2
C subaddressand control tables.
I.5 - Sync Processor
TheinternalsyncprocessorallowstheTDA9109/N
to accept:
- separated horizontal & vertical TTL-compatible
sync signal,
- composite horizontal & vertical TTL-compatible
sync signal.
TDA9109/N
16/32
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