參數(shù)資料
型號: TDA9109N
廠商: 意法半導體
英文描述: LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述: 低費用偏轉處理器多同步監(jiān)測儀
文件頁數(shù): 6/32頁
文件大?。?/td> 303K
代理商: TDA9109N
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
DD
V
IN
Parameter
Value
13.5
5.7
4.0
5.5
6.4
8.0
V
CC
V
DD
2
300
-40, +150
+150
0, +70
Unit
V
V
V
V
V
V
V
V
kV
V
o
C
o
C
o
C
Supply Voltage (Pin 29)
Supply Voltage (Pin 32)
Max Voltage on Pin 4
Pin 9
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pin 10, 18, 23, 24, 25, 26, 28
Pins 1, 2, 3, 30, 31
VESD
ESD susceptibility
EIAJ Norm,200pF Discharge through 0
Storage Temperature
Junction Temperature
Operating Temperature
Human Body Model,100pF Discharge through 1.5k
T
stg
T
j
T
oper
9
THERMAL DATA
Symbol
R
th (j-a)
Parameter
Value
65
Unit
o
C/W
Junction-Ambient Thermal Resistance
Max.
9
SYNC PROCESSOR
Operating Conditions
(V
DD
= 5V,T
amb
= 25
o
C)
Symbol
HsVR
MinD
Mduty
VsVR
VSW
VSmD
VextM
I
HLOCKOUT
ElectricalCharacteristics
(V
DD
= 5V,T
amb
= 25
o
C)
Symbol
VINTH
Horizontal and Vertical Input Logic Level
(Pins 1, 2)
RIN
Horizontal and Vertical Pull-Up Resistor
TfrOut
Fall and Rise Time, Output CMOS Buffer
VHlock
Horizontal1st PLLLock OutputStatus(Pin3)
Parameter
Test Conditions
Pin 1
Pin 1
Pin 1
Pin 2
Pin 2
Pin 2
Pin 1
Pin3
Min.
0
0.7
Typ.
Max.
5
Unit
V
μ
s
%
V
μ
s
%
μ
s
μ
A
Voltage on H/HVIN Input
Minimum Horizontal Input Pulses Duration
Maximum Horizontal Input Signal Duty Cycle
Voltage on VSYNCIN
Minimum Vertical Sync Pulse Width
Maximum Vertical SyncInput Duty Cycle
Maximum VerticalSync Widthon TTLH/Vcomposite
Sink and Source Current
25
5
0
5
15
750
250
Parameter
Test Conditions
Low Level
High Level
Pins 1, 2
Pin 3, C
OUT
= 20pF
Locked, I
= -250
μ
A
Unlocked, I
LOCKOUT
= +250
μ
A
C0 = 820pF
Min.
Typ.
Max.
0.8
Unit
V
V
k
ns
V
V
%
2.2
200
200
0.5
4.4
26
0
5
VoutT
Extracted Vsync Integration Time (% of T
H
)
on H/V Composite (see Note 1)
Note 1 : T
H
is the horizontal period.
35
I
2
C READ/WRITE
(seeNote 2)
ElectricalCharacteristics
(V
DD
= 5V,T
amb
= 25
o
C)
Symbol
I
2
C PROCESSOR
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Fscl
Tlow
Thigh
Vinth
VACK
Note 2 :
See also I
2
C Table Control and I
2
C Sub Address Control.
Maximum Clock Frequency
Low period of the SCL Clock
High period of the SCL Clock
SDA and SCL Input Threshold
Acknowledge Output Voltage on SDA input with 3mA
Pin 30
Pin 30
Pin 30
Pins 30,31
Pin 31
400
kHz
μ
s
μ
s
V
V
1.3
0.6
2.2
0.4
9
TDA9109/N
6/32
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