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參數(shù)資料
| 型號： | TDA9109N |
| 廠商： | 意法半導體 |
| 英文描述： | LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低費用偏轉(zhuǎn)處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 303K |
| 代理商： | TDA9109N |
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II.2 - PLL1
The PLL1 consists of a phase comparator, an
external filter and a voltage-controlled oscillator
(VCO). The phase comparator is a ”phase fre-
quency” type designedin CMOS technology.This
kind of phase detector avoids locking on wrong
frequencies. It is followed by a ”charge pump”,
composedof twocurrent sources : sunk and sour-
ced (typically I = 1mAwhen locked and I = 140
μ
A
whenunlocked).Thisdifferencebetweenlock/unlock
allows smooth catching of the horizontal frequency
by PLL1. This effect is reinforced by an internal
original slow down system when PLL1 is locked,
avoiding the horizontal frequency changing too
quickly.The dynamicbehaviourof PLL1is fixed by
an externalfilter whichintegratesthe currentof the
charge pump. A ”CRC” filter is generally used
(seeFigure 7).
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase compa-
rator.The inhibition is done by a switch located
between the charge pump and the filter (see Fig-
7
PLL1F
1
μ
F
4.7
μ
F
1.8k
9
Figure 7
OPERATINGDESCRIPTION
(continued)
ure 8). The VCO uses an external RC network. It
delivers a linear sawtoothobtained by the charge
and the discharge of the capacitor, with a current
proportionalto the current in the resistor. The typi-
cal thresholdsof the sawtoothare 1.6V and6.4V.
The control voltageofthe VCOis between 1.33V
and 6V (see Figure 9). The theorical frequency
range of this VCO is in the ratio of 1 to 4.5.
The effective frequency range has to be smaller
(1 to 4.2) due to clamp intervention on the filter
lowest value.
6
7
Loop
Filter
R0
1.6V
6.4V
5
C0
6.4V
1.6V
0 0.875T
H
T
H
RS
FLIP FLOP
(1.3V < V
< 6V)
7
I
0
2
4 I
0
I
0
9
Figure 9 :
Detailsof VCO
LOCKDET
COMP1
INPUT
INTERFACE
H/HVIN
High
CHARGE
PUMP
Low
PLL
INHIBITION
VCO
7
6
5
PLL1F
R0
C0
PHASE
ADJUST
E2
I
2
C
HPOS
Adj.
OSC
Tramext
Tramext
I
2
C
Forced
Frequency
Lock/Unlock
Status
8
HPOSITION
1
9
Figure 8 :
BlockDiagram
TDA9109/N
18/32
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