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參數(shù)資料
| 型號： | TDA9109N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低費用偏轉(zhuǎn)處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大小： | 303K |
| 代理商： | TDA9109N |
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HORIZONTAL SECTION
Operating Conditions
Symbol
VCO
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
R
0(Min.)
C
0(Min.)
F
(Max.)
OUTPUT SECTION
I12m
HOI
Minimum Oscillator Resistor
Minimum Oscillator Capacitor
Maximum Oscillator Frequency
Pin 6
Pin 5
6
k
pF
kHz
390
150
Maximum Input Peak Current
Horizontal Drive Output Maximum Current
Pin 12
Pin 26, Sunk current
5
30
mA
mA
ElectricalCharacteristics
(V
CC
= 12V,T
amb
= 25
o
C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY AND REFERENCE VOLTAGES
V
CC
V
DD
I
CC
I
DD
V
REF-H
V
REF-V
I
REF-H
I
REF-V
1st PLL SECTION
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Horizontal Reference Voltage
Vertical Reference Voltage
Max. Sourced Current on V
REF-H
Max. Sourced Current on V
REF-V
Pin 29
Pin 32
Pin 29
Pin 32
Pin 13, I = -2mA
Pin 21, I = -2mA
Pin 13
Pin 21
10.8
4.5
12
5
50
5
8
8
13.2
5.5
V
V
mA
mA
V
V
mA
mA
7.4
7.4
8.6
8.6
5
5
HpolT
Delay Time for detecting polarity change
(see Note 3)
VCO Control Voltage (Pin 7)
Pin 1
0.75
ms
V
VCO
V
REF-H
= 8V
f
0
f
H
(Max.)
1.3
6.2
17.1
V
V
Vcog
VCO Gain (Pin7)
R
= 6.49k
, C
0
= 820pF,
dF/dV = 1/11R
0
C
0
% of Horizontal Period
Sub-Address 01
Byte x1111111
Byte x1000000
Byte x0000000
PLL1 is Unlocked
PLL1 is Locked
R
0
= 6.49k
, C
0
= 820pF,
f
0
= 0.97/8R
0
C
0
kHz/V
Hph
Horizontal Phase Adjustment(see Note 4)
Horizontal Phase SettingValue (Pin 8)(seeNote4)
Minimum Value
Typical Value
Maximum Value
PLL1 Filter Current Charge
±
10
%
Vbmin
Vbtyp
Vbmax
IPll1U
IPll1L
f
0
2.8
3.4
4.0
±
140
±
1
22.8
V
V
V
μ
A
mA
kHz
Free Running Frequency
df0/dT
Free Running Frequency Thermal Drift
(No drift on external components) (seeNote 5)
PLL1 Capture Range (see Note 6)
-150
ppm/C
CR
R
0
= 6.49k
, C
0
= 820pF,
from f
+0.5kHz to 4.5f
0
f
H
(Min.)
f
H
(Max.)
Sub-Address 02
90
25
kHz
kHz
FF
Forced Frequency
FF1 Byte 11xxxxxx
FF2 Byte 10xxxxxx
2f0
3f0
Notes : 3. This delay is mandatoryto avoid a wrong detectionof polarity change in the case of a composite sync.
4. See Figure 10 for explanation of reference phase.
5. These parametersare not tested on each unit. They are measured during our internalqualification.
6. This PLL capturerange may be obtained only iff
is adjusted (for instanceby adjusting R
0
) .If not, more marginmust be provided
between f
H
(Min.) and f
0
, to cope with the components spread.
9
TDA9109/N
7/32
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