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參數(shù)資料
| 型號： | TDA9109N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低費(fèi)用偏轉(zhuǎn)處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 303K |
| 代理商： | TDA9109N |
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OPERATINGDESCRIPTION
(continued)
Figure 15
Horizontal Flyback
Internal Trigged
Horizontal Flyback
Horizontal Focus
Cap Sawtooth
Horizontal Dynamic
Focus Parabola
Output
4.7V
2V
2V
400ns
9
III - VERTICAL PART
III.1- Function
When the synchronizationpulse is not present,an
internal current source sets the free running fre-
quency.For an external capacitor, C
OSC
= 150nF,
the typical free running frequencyis 100Hz.
The typical free running frequency can be calcu-
lated by :
f
0
(
Hz
) =
1.5
10
5
1
C
OSC
A negative or positive TTL level pulse applied on
Pin2 (VSYNC)as wellasa TTLcompositesyncon
Pin 1 can synchronize the ramp in the range
[fmin, fmax].Thisfrequencyrangedependson the
external capacitor connected on Pin 22.
A 150nF (
±
5%) capacitor is recommended for
50Hz to 165Hzapplications.
The typical maximum and minimum frequency,at
25
o
C and without any correction (S correction or
C correction), can be calculatedby :
f
(Max.)
= 2.5 x f
0
and f
(Min.)
= 0.33 x f
0
If S or C corrections are applied, these values are
slighty affected.
If a synchronization pulse is applied, the internal
oscillator is synchonized immediately but its am-
plitude changes. An internal correction then ad-
justs it in less thanhalf a second.The top value of
theramp(Pin22)is sampledontheAGCcapacitor
(Pin 20) at each clock pulse and a transconduc-
tance amplifier modifies thecharge current of the
capacitor in such a way to make the amplitude
again constant.
Thereadstatusregister providestheverticalLock-
Unlock and the vertical sync polarity information.
We recommend the use of an AGC capacitorwith
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF
±
5% capacitor value on
Pin 20 (VAGC).
III.2 - I
2
C Control Adjustments
S and C correction shapes can then be added
to this ramp. These frequency independent S
and C corrections are generated internally.
Their amplitudes are adjustableby their respec-
tive I
2
C registers. They can also be inhibited by
their select bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.
The adjustedramp is availableon Pin23 (V
OUT
) to
drive an external power stage.
The gain of this stage can be adjusted (
±
25%)
dependingon its register value.
The mean value of this ramp is driven by its own
I
2
C register (vertical position). Its value is
VPOS = 7/16
V
REF-V
±
300mV.
Usually VOUTis sent througha resistive dividerto
the inverting input of the booster. Since VPOS
derives from V
REF-V
, the bias voltage sent to the
non-inverting input of the booster should also de-
rive from V
REF-V
to optimizethe accuracy(see Ap-
plication Diagram).
III.3 - VerticalMoiré
By using the vertical moiré, VPOS can be modu-
latedfromframetoframe.Thisfunctionis intended
to cancelthefringeswhichappearwhen lineto line
intervalis very close to the CRTvertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-offvia the control bit D7.
TDA9109/N
21/32
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