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參數(shù)資料
| 型號： | TH58100FT |
| 廠商： | Toshiba Corporation |
| 英文描述： | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 馬鞍山暫定東芝數(shù)字集成電路硅柵CMOS |
| 文件頁數(shù)： | 5/43頁 |
| 文件大?。?/td> | 421K |
| 代理商： | TH58100FT |
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TH58100FT
2001-03-05 5/43
Note: (1)
CE
High to Ready time depends on the pull-up resistor tied to the
(Refer to Application Note (9) toward the end of this document.)
BY
/
RY
pin.
(2) Sequential Read is terminated when t
CEH
is greater than or equal to 100 ns. If the
RE
to
CE
delay
is less than 30 ns,
BY
/
RY
signal stays Ready.
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta 0° to 70°C, V
CC
2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NOTES
t
PROG
Programming Time
200
1000
s
t
DBSY
Dummy Busy Time for Multi Block
Programming
2
10
s
t
MBPBSY
Multi Block Program Busy Time
200
1000
s
N
Number of Programming Cycles on Same
Page
3
(1)
t
BERASE
Block Erasing Time
2
10
ms
(1): Refer to Application Note (12) toward the end of this document.
: 0 to 30 ns
Busy signal is not output.
A
CE
RE
t
CEH
100 ns
*
525
Busy
BY
/
RY
*
: V
IH
or V
IL
A
526
527
t
CRY
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