參數(shù)資料
型號(hào): THS8083-95CPZP
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁(yè)數(shù): 36/61頁(yè)
文件大?。?/td> 239K
代理商: THS8083-95CPZP
4–1
4 Parameter Measurement Information
All timing diagrams are shown for operation with internal PLL clock at phase 0, and ADCCLK2 non-inverted and
non-divided-by-2.
4.1
Timing Diagram – 24-Bit Parallel Mode
This mode outputs data on the three channels simultaneously in single-pixel mode. DATACLK1 is at the sampling
clock frequency; output bus B remains high-impedance.
DATACLK
CH1_OUTA[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH1_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
7 ADCCLK2 Cycles Latency
01
02
7 ADCCLK2
cycles latency
last samples from previous line
pix 01
pix 02
ADCCLK2
OE
<DHS_MODE> = 0 –> DHS width is 1
ADCCLK2 period
<DHS_MODE> = 1 –>
width equal to width of
HS input
DHS
(DHS_POL=0 assumed –
inverted polarity otherwise)
tPLH(OE)
last samples from previous line
tPHL(OE)
tsu(OUT)
th(OUT)
tsu(DHS)
th(DHS)
01
02
01
02
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