參數(shù)資料
型號： THS8083-95CPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁數(shù)： 6/61頁
文件大小： 239K
代理商： THS8083-95CPZP
1–8
1.7
THS8083 Terminal Functions Order (Continued)
TERMINAL
I/O/B
TYPE
DESCRIPTION
NAME
NO.
I/O/B
TYPE
DESCRIPTION
DIGITAL CONTROL I/O
SCL
3
B
D
Clock for I2C. Although the device is an I2C slave, this signal can be held low by the device to
signal contention, therefore it is flagged bidirectional.
SDA
4
B
D
Serial data for I2C
I2CA
5
I
D
Address select for I2C
0 = LSB of device address 0
1 = LSB of device address 1
EXT_CLP
99
I
D
External clamp timing pulse. Positive polarity required.
HS
1
I
D
Reference clock input for PLL (horizontal sync input). Polarity selectable via I2C register
<HS_POL>. 5 V tolerant input
VS
2
I
D
Vertical sync input. Polarity selectable via I2C register <VS_POL>. 5 V tolerant input
DHS
55
O
D
Display horizontal sync. This output can be generated as either a delayed version of input
HS or as output pulse from the PLL feedback divider. See Display Horizontal Sync section
in Functional Description.
CS/TEST1
78
O
A/D
Composite sync output. This output will produce a 3-V logic-compatible sliced output of
CH1. When present and enabled, CS will carry the composite sync embedded in Ch1. See
Composite Sync Slicer section in Functional Description. For TI internal testing, this pin
can also be configured as a test pin. Leave unconnected when CS output signal is not
used.
LOCK
100
O
D
Lock detect output
0 = unlocked
1 = locked
PFD_FREEZE
98
I
D
Freezes the PLL output frequency by stopping the PFD output (i.e., keeping last increment
to DTO). See section 2.3
Composite Sync Slicer.
0 = updating
1 = frozen
OE
71
I
D
Output enable for data output busses A and B. Data outputs are active only when OE = L
and the corresponding bus is active for the current output formatter mode (register
OFM_CTRL). When data outputs are not active or when DVDD = 0 V, data output is Hi-Z.
The clock outputs are not affected by OE.
0 = enabled
1 = disabled
RESET
76
I
D
General chip reset (active low). The reset is a synchronous reset. Therefore, a master clock on
XTL1–MCLK needs to be present for proper reset.
TEST I/O
CS/TEST1
78
O
A/D
See description for this terminal under DIGITAL CONTROL I/O higher.
TEST2
79
O
A/D
Test mode analog output 2. Leave unconnected for normal use.
SCAN_TEST
77
I
D
Input for scan-path activation:
0 = disabled
1 = enabled.
This pin MUST be tied low for normal operation and is of use for TI internal testing only.
UNUSED PINS
NC
80, 86,
87, 93,
94
I
A
Not connected. Tie to a fixed high or low level on board.
I = input to device: O = output from device B = bidirectional
A = analog pin: D = digital pin
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相關代理商/技術參數(shù)
參數(shù)描述
THS8083A 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 8 BIT 80 MSPS 3.3V VIDEO AND GRAPHICS
THS8083A95 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS
THS8083A95PZP 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
THS8083APZP 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Triple 8B 80 MSPS 3.3V YUV/RGB RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
THS8083APZP 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083
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