參數(shù)資料
型號(hào): THS8083-95CPZP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁數(shù): 37/61頁
文件大?。?/td> 239K
代理商: THS8083-95CPZP
4–2
4.2
Timing Diagram – 16-Bit Parallel Mode
This is the ITU.BT–601 style mode that will typically be used in YUV operation of the part with a Y analog input
connected to the Ch1 input of THS8083, Cb from Ch.2 input, and Cr from Ch.3 input. The DATACLK1 output is at
the sampling clock frequency and Ch3 remains unused. Output bus B of all channels is high impedance. The DHS
signal can be used to uniquely identify Cb from Cr output data.
DATACLK
CH1_OUTA[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH1_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
7 ADCCLK2 cycles latency
01(Cb)
02
DHS
(DHS_POL=0 assumed –
inverted polarity otherwise)
7 ADCCLK2
cycles latency
01(Cr)
03(Cb)
Cb: from Ch.2 input
Cr: from Ch.3 input
last samples from previous line
pix 01
pix 02
ADCCLK2
OE
<DHS_MODE> = 0 –> DHS width is 1
<DHS_MODE> = 1 –> width equal to
03
last samples from previous line
tPLH(OE)
tPHL(OE)
tsu(OUT)
th(OUT)
01
width of HS input
ADCCLK2 period
th(DHS)
tsu(DHS)
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