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參數資料
| 型號： | TLE6266G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | 18 MM, PLASTIC, SOP-28 |
| 文件頁數： | 16/50頁 |
| 文件大?。?/td> | 1020K |
| 代理商： | TLE6266G |
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Datasheet TLE 6266 G
Version 2.21
23
July 29th, 2005
Figure 8
Cyclic Wake with CAN Message Wake-up
7.2
Wake-Up via Wake Pin
CANL is pulled to Vs. A signal transition at the wake pin WK from LOW to HIGH (rising
edge) causes a wake up and automatic transition into the cyclic HS ON mode (see
Figure 9). HS3 is activated again and also the long open window of the watchdog
mechanism. The watchdog has to be triggered correctly from that time on. If the signal
at the PWM pin makes a HIGH to LOW transition, the device switches to HS OFF again.
This wake up via the wake pin is comming from an external circuitry (switch, etc.) and
is not flagged by the RxD.
Normal Mode
Cyclic HS ON
Cyclic HS OFF
SPI
cyclic HS
ON
Mode State
SPI word*
t
CANL
PWM
HS3
t
Watchdog trigger bit
=SPI bit0**
SPI
normal
mode
PWM
trigger
Window watchdog***
CSN,
Normal Mode
closed
window
open
window
open
window
closed
window
long open window
Cyclic HS ON
Bus
Wake
trigger
long open window
Cyclic HS ON
closed
window
open
window
closed
window
open
window
missing trigger =
timeout =
Watchdog Reset
t
long open window
Normal Mode
Vbat Stdby
CAN Bus message
PWM trigger
Input filtering time t
IFT
Watchdog reset pulse time t
WDR
** bit0 is transfered with the SPI input word
BUT
the watchdog trigger is set, after readout of
the SPI input bit = CSN LOW to HIGH
(see arrows at CSN signal)
* for the exact timing relations between CSN
and SPI-DI and -DO word please look at
datasheet fig. 11,12,13,14,15
*** for a correct watchdog triggering:
closed window must always exceed 12 cycles
open window is max. 20 cycles
long open window is max. 128 cycles
otherwise
a watchdog reset will be generated
SPI
normal
mode
SPI
cyclic HS
ON
CANH
Vcc
Vs
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