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參數(shù)資料
| 型號： | TLE6266G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | 18 MM, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 8/50頁 |
| 文件大?。?/td> | 1020K |
| 代理商： | TLE6266G |
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Datasheet TLE 6266 G
Version 2.21
16
July 29th, 2005
Figure 6
LDO activation flowchart for the cyclic wake HS OFF mode
6.6
3V-Supervisor
This feature is useful e.g. to monitor that the RAM data of the microcontroller might be
damaged (prewarning) or the application is connected to VS the first time(OEM
production line).
The 3V-supervisor is available in all operation modes and has to be activated via the SPI
input bit 7in normal operation mode. If the output voltage falls below the 3V-supervisor
threshold VST, an internal flip-flop is set LOW and the SPI monitors this by setting output
bit 7LOW. If the output voltage Vcc> 3V-supervisor threshold VST, the SPI output bit 7 is
set HIGH.
The 3V supervisor uses a comparator to monitor the voltage. Additional, there is a
possibility to disable this comparator in order to reduce the current consumption. To do
this, set SPI input bit 15 first and in the next step set SPI input bit 7.
6.7
SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see Table 6) is read in via the data
input DI, and this is synchronized with the clock input CLK supplied by the C. The
diagnosis word appears synchroniously at the data output DO (see Table 7).
V
cc > load threshold
V
CC TH ?
Monitor V
cc in Cyclic wake
HS OFF Mode
Charge of V
cc
(Switch on LDO)
Yes
Vcc
No
RESET after filtering-
time
5
4
V
CC TH
Charge Diagram
Vcc
t
CHARGE
V
RESET TH
V
cc< reset threshold
V
RESET TH
for t > 3s ?
No
1ms
Charge of V
cc for 1ms
(Switch on LDO)
Load gets
activated
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