參數(shù)資料
型號: TLV320AIC33IZQE
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝: 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80
文件頁數(shù): 10/93頁
文件大?。?/td> 1427K
代理商: TLV320AIC33IZQE
OVERVIEW
HARDWARE RESET
DIGITAL CONTROL SERIAL INTERFACE
SPI CONTROL MODE
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7bit Register Address
Write
8bit Register Data
/SS
SCLK
MOSI
MISO
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
The TLV320AIC33 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended
for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
Available in a 5x5mm 80-ball BGA (with 51 balls actually used) and 7x7mm 48-lead QFN, the product integrates
a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered,
portable applications.
The TLV320AIC33 consists of the following blocks:
Stereo audio multi-bit delta-sigma DAC (8 kHz – 96 kHz)
Stereo audio multi-bit delta-sigma ADC (8 kHz – 96 kHz)
Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, de-emphasis)
Six audio inputs
Four high-power audio output drivers (headphone/speaker drive capability)
Three fully differential line output drivers
Fully programmable PLL
Headphone/headset jack detection with interrupt
Communication to the TLV320AIC33 for control is pin-selectable (using the SELECT pin) as either SPI or I2C.
The SPI interface requires that the Slave Select signal (MFP0) be driven low to communicate with the
TLV320AIC33. Data is then shifted into or out of the TLV320AIC33 under control of the host microprocessor,
which also provides the serial data clock. The I2C interface supports both standard and fast communication
modes, and also enables cascading of up to four multiple codecs on the same I2C bus through the use of two
pins for addressing (MFP0, MFP1).
The TLV320AIC33 requires a hardware reset after power-up for proper operation. After all power supplies are at
their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the 'AIC33 may not respond properly to register reads/writes.
The TLV320AIC33 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SELECT pin. For SPI, SELECT should be tied high; for I2C, SELECT should be tied low. It is not
recommended to change the state of SELECT during device operation.
Figure 15. SPI Write
18
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC33
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