CONTINUOUS READ / WRITE OPERATION
I
2C CONTROL MODE
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access
registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to
register 0, the page control register, to change the active page back to page 0. After a recommended read of the
page control register, all further read/write operations to addresses 1 to 127 will now access page 0 registers
again.
Limitation on Register Writing
When writing registers in SPI mode related to the audio output drivers mux, mix, gain configuration, etc., do not
use the auto-increment mode. In addition, between two successive writes to these registers, the host should
keep MFP0 (SPI chip select) high for at least 6.25us, to ensure that the register writes have occurred properly.
The TLV320AIC33 includes the ability to read/write registers continuously, without needing to provide an address
for every register accessed. In SPI mode, a continuous write is executed by transitioning MFP0 (SPI chip select)
low to start the frame, sending the first 8-bit command word to read/write a particular register, and then sending
multiple bytes of register data, intended for the addressed register and those following. A continuous read is
done similarly, with multiple bytes read in from the addressed register and the following registers on the page.
When the MFP0 (SPI chip select) pin is transitioned high again, the frame ends, as does the continuous
read/write operation. A new frame must begin again with a new command word, to start the next bus transaction.
Note that this continuous read/write operation does not continue past a page boundary. The user should not
attempt to read/write past the end of a page, since this may result in undesirable operation.
The TLV320AIC33 supports the I2C control protocol when the SELECT pin is tied low, using 7-bit addressing and
capable of both standard and fast modes. TLV320AIC33 supports the I2C control protocol using 7-bit addressing
and capable of both standard and fast modes. For I2C fast mode, note that the minimum timing for each of
tHD-STA, tSU-STA, and tSU-STO is 2.0
s, as seen in Figure 17. When in I2C control mode, the TLV320AIC33 can be configured for one of four different addresses, using the multifunction pins MFP0 and MFP1, which
control the two LSBs of the device address. The 5 MSBs of the device address are fixed as 00110 and cannot be
changed, while the two LSBs are given by MFP1:MFP0. This results in four possible device addresses:
I2C slave Device Addresses for MFP1, MFP0 Settings
MFP1
MFP0
Device Address
0
0011000
0
1
0011001
1
0
0011010
1
0011011
20
Copyright 2006–2008, Texas Instruments Incorporated