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參數(shù)資料
| 型號： | TLV320AIC33IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 57/93頁 |
| 文件大?。?/td> | 1427K |
| 代理商： | TLV320AIC33IZQE |
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SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
Page 0 / Register 40:
High Power Output Stage Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D3–D2
R/W
00
LINE2R Bypass Path Control
00: LINE2R bypass is disabled
01: LINE2R bypass uses LINE2RP single-ended
10: LINE2R bypass uses LINE2RM single-ended
11: LINE2R bypass uses LINE2RP/M differentially
D1–D0
R/W
00
Output Volume Control Soft-Stepping
00: Output soft-stepping = one step per Fs
01: Output soft-stepping = one step per 2Fs
10: Output soft-stepping disabled
11: Reserved. Do not write this sequence to these register bits.
Page 0 / Register 41:
DAC Output Switching Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Left DAC Output Switching Control
00: Left DAC output selects DAC_L1 path
01: Left DAC output selects DAC_L3 path to left line output driver
10: Left DAC output selects DAC_L2 path to left high power output drivers (1)
11: Reserved. Do not write this sequence to these register bits.
D5–D4
R/W
00
Right DAC Output Switching Control
00: Right DAC output selects DAC_R1 path
01: Right DAC output selects DAC_R3 path to right line output driver
10: Right DAC output selects DAC_R2 path to right high power output drivers (1)
11: Reserved. Do not write this sequence to these register bits.
D3–D2
R/W
00
Reserved. Write only zeros to these bits.
D1–D0
R/W
00
DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
(1)
When using the DAC direct paths (DAC_L2 and DAC_R2), the signal will be gain up by a factor of -1dB.
Page 0 / Register 42:
Output Driver Pop Reduction Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
Output Driver Power-On Delay Control
0000: Driver power-on time = 0-
sec
0001: Driver power-on time = 10-
sec
0010: Driver power-on time = 100-
sec
0011: Driver power-on time = 1-msec
0100: Driver power-on time = 10-msec
0101: Driver power-on time = 50-msec
0110: Driver power-on time = 100-msec
0111: Driver power-on time = 200-msec
1000: Driver power-on time = 400-msec
1001: Driver power-on time = 800-msec
1010: Driver power-on time = 2-sec
1011: Driver power-on time = 4-sec
1100–1111: Reserved. Do not write these sequences to these register bits.
D3-D2
R/W
00
Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0-msec
01: Driver ramp-up step time = 1-msec
10: Driver ramp-up step time = 2-msec
11: Driver ramp-up step time = 4-msec
D1
R/W
0
Weak Output Common-mode Voltage Control
0:
Weakly driven output common-mode voltage is generated from resistor divider off the AVDD
supply
1:
Weakly driven output common-mode voltage is generated from bandgap reference
D0
R/W
0
Reserved. Write only zero to this register bit.
60
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC33
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| TLV320AIC33IZQE | 制造商:Texas Instruments 功能描述:AUDIO CODEC IC ((NW)) |
| TLV320AIC33IZQER | 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 7 Otp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC33NIZQE | 制造商:Texas Instruments 功能描述: |
| TLV320AIC33NIZQER | 制造商:Texas Instruments 功能描述: |
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