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參數(shù)資料
| 型號： | TLV320AIC33IZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80 |
| 文件頁數(shù)： | 25/93頁 |
| 文件大?。?/td> | 1427K |
| 代理商： | TLV320AIC33IZQER |
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AUTOMATIC GAIN CONTROL (AGC)
www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 Fs to the final output sampling rate of Fs. The decimation filter provides a linear phase
output response with a group delay of 17/Fs. The –3 dB bandwidth of the decimation filter extends to 0.45 Fs
and scales with the sample rate (Fs). The filter has minimum 75dB attenuation over the stopband from 0.55 Fs to
64 Fs. Independent digital highpass filters are also included with each ADC channel, with a corner frequency that
can be independently set to three different settings or can be disabled entirely.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC33 integrates a second order
analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient anti-aliasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see registers Page-0/Reg-19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and upon
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power down register is written to ensure the soft-stepping to mute has completed. When the ADC
powerdown flag is no longer set, the audio master clock can be shut down.
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry
automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several
programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum
PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses
the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the
nominal amplitude of the output signal.
Note that completely independent AGC circuitry is included with each ADC channel with entirely independent
control over the algorithm from one channel to the next. This is attractive in cases where two microphones are
used in a system, but may have different placement in the end equipment and require different dynamic
performance for optimal system operation.
Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC33 allows programming of eight different target gains, which can be programmed from –5.5 dB to
–24 dB relative to a full-scale signal. Since the device reacts to the signal absolute average and not to peak
levels, it is recommended that the larger gain be set with enough margin to avoid clipping at the occurrence of
loud sounds.
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 8 ms to 20 ms.
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied
in the range from 100 ms to 500 ms.
Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it
as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every FS and sets the noise threshold
flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This
ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm
is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This
operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling
between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is
set, the status of gain applied by the AGC and the saturation flag should be ignored.
Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
programmed noise threshold. It can be programmed from 0 dB to +59.5 dB in steps of 0.5 dB.
Copyright 2006–2008, Texas Instruments Incorporated
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Product Folder Link(s): TLV320AIC33
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| TLV320AIC33NIZQE | 制造商:Texas Instruments 功能描述: |
| TLV320AIC33NIZQER | 制造商:Texas Instruments 功能描述: |
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