參數(shù)資料
型號： TLV320AIC33IZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80
文件頁數(shù)： 48/93頁
文件大?。?/td> 1427K
代理商： TLV320AIC33IZQER
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
Page 0 / Register 19:
LINE1L to Left ADC Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D6–D3
R/W
1111
LINE1L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the left ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the left ADC PGA
D2
R/W
0
Left ADC Channel Power Control
0: Left ADC channel is powered down
1: Left ADC channel is powered up
D1–D0
R/W
00
Left ADC PGA Soft-Stepping Control
00: Left ADC PGA soft-stepping at once per Fs
01: Left ADC PGA soft-stepping at once per two Fs
10–11: Left ADC PGA soft-stepping is disabled
Page 0 / Register 20:
LINE2L to Left(1) ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2L Single-Ended vs Fully Differential Control
If LINE2L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2L is configured in single-ended mode
1: LINE2L is configured in fully differential mode
D6–D3
R/W
1111
LINE2L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2L to the left ADC PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE2L is not connected to the left ADC PGA
D2
R/W
0
Left ADC Channel Weak Common-Mode Bias Control
0:
Left ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1:
Left ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1-D0
R
00
Reserved. Write only zeros to these register bits
(1)
LINE1R SEvsFD control is available for both left and right channels. However this setting must be same for both the channels.
Page 0 / Register 21:
LINE1R to Left ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
52
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC33
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