參數(shù)資料
型號： TLV320AIC33IZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80
文件頁數(shù)： 46/93頁
文件大?。?/td> 1427K
代理商： TLV320AIC33IZQER
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
Page 0 / Register 14:
Headset / Button Press Detection Register B (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D3(1)
R/W
0
Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudo-differential output configuration is not being used
1: A stereo pseudo-differential output configuration is being used
D2–D0
R
000
Reserved. Write only zeros to these bits.
Page 0 / Register 15:
Left ADC PGA Gain Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
1
Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
D6-D0
R/W
0000000
Left ADC PGA Gain Setting
0000000: Gain = 0.0-dB
0000001: Gain = 0.5-dB 0000010: Gain = 1.0-dB
…
1110110: Gain = 59.0-dB
1110111: Gain = 59.5-dB
1111000: Gain = 59.5-dB
…
1111111: Gain = 59.5-dB
Page 0 / Register 16:
Right ADC PGA Gain Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
1
Right ADC PGA Mute
0: The right ADC PGA is not muted
1: The right ADC PGA is muted
D6-D0
R/W
0000000
Right ADC PGA Gain Setting
0000000: Gain = 0.0-dB
0000001: Gain = 0.5-dB
0000010: Gain = 1.0-dB
…
1110110: Gain = 59.0-dB
1110111: Gain = 59.5-dB
1111000: Gain = 59.5-dB
…
1111111: Gain = 59.5-dB
Page 0 / Register 17:
MIC3L/R to Left ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
1111
MIC3L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the left ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the left ADC PGA
50
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC33
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