參數(shù)資料
型號(hào)： TLV320AIC33IZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80
文件頁(yè)數(shù)： 68/93頁(yè)
文件大?。?/td> 1427K
代理商： TLV320AIC33IZQER
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ........................................................................................................................................... www.ti.com
Page 0 / Register 86:
LEFT_LOP/M Output Level Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
LEFT_LOP/M Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
R/W
0
LEFT_LOP/M Mute
0: LEFT_LOP/M is muted
1: LEFT_LOP/M is not muted
D2
R/W
0
Reserved. Write only zero to this register bit.
D1
R
0
LEFT_LOP/M Volume Control Status
0: All programmed gains to LEFT_LOP/M have been applied
1: Not all programmed gains to LEFT_LOP/M have been applied yet
D0
R/W
0
LEFT_LOP/M Power Control
0: LEFT_LOP/M is not fully powered up
1: LEFT_LOP/M is fully powered up
Page 0 / Register 87:
LINE2L to RIGHT_LOP/M Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to RIGHT_LOP/M
1: LINE2L is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
LINE2L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 88:
PGA_L to RIGHT_LOP/M Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP/M
1: PGA_L is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
PGA_L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 89:
DAC_L1 to RIGHT_LOP/M Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP/M
1: DAC_L1 is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
DAC_L1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 90:
LINE2R to RIGHT_LOP/M Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to RIGHT_LOP/M
1: LINE2R is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
LINE2R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
70
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC33
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