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參數(shù)資料
| 型號： | TMP90C401 |
| 廠商： | Toshiba Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Multifunction Timer/Event Counter(高速、先進的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器）) |
| 中文描述： | 采用先進的CMOS高速8位微控制器，集成8位CPU，內(nèi)存，光盤，通用串行接口，多功能定時器/事件計數(shù)器（高速，先進的的CMOS 8位微控制器（芯片集成了8位的CPU，ROM和RAM內(nèi)存，通用串行接口，多功能定時器/事件計數(shù)器）） |
| 文件頁數(shù)： | 14/100頁 |
| 文件大?。?/td> | 2591K |
| 代理商： | TMP90C401 |
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14
TOSHIBA CORPORATION
TMP90C400/401
3.3 Interrupt Functions
The TMP90C400 supports a general purpose interrupt processing
mode for internal and external interrupt requests and a micro
DMA processing mode that enables automatic data transfer
by the CPU. After the reset state is released, all interrupt
requests are processed in the general purpose interrupt
processing mode. However, they can be processed in the
micro DMA processing mode by using a DMA enable register
to be described later.
Figure 3.3 (1) is a flowchart of the interrupt response
sequence.
Figure 3.3 (1). Interrupt Response Flowchart
When an interrupt is requested, the request is to the inter-
rupt transmitted to the CPU via an internal interrupt controller.
The CPU starts the interrupt processing if it is a non-maskable
or maskable interrupt requested in the EI state (interrupt enable
flag (IFF = “1”). However, a maskable interrupt requested in the
DI state (IFF = “0”) is ignored. An interrupt request is sampled by
the CPU at the falling edge of the CLK signal in the last bus
cycle of each instruction.
By receiving an interrupt, the CPU reads out the interrupt
vector from the internal interrupt controller to find out the interrupt
source.
Then, the CPU checks if the interrupt requests the general
purpose interrupt processing or the micro DMA processing,
and proceeds to each processing.
As the reading of an interrupt vectors is performed in the
internal operating cycles, the bus cycle results in dummy
cycles.
3.3.1 General-purpose Interrupt Processing
A general-purpose interrupt is processed as shown in Figure
3.3 (2).
The CPU stores the contents of the program counter PC
and the register pair AF (including the interrupt enable flag (IFF)
before an interrupt) into the stack, and resets the interrupt
enable flag IFF to “0” (disable interrupts). In then transfers the
value of the interrupt vector “V” to the program counter, and
the processing jumps to an interrupt processing program.
The overhead for the entire process from accepting an
interrupt to jumping to an interrupt processing program is 20
states.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP90C401F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C401N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C441 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| TMP90C441F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C441N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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