參數(shù)資料
型號(hào): TMP90C401
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM,ROM,General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器(芯片集成了8位CPU,ROM,RAM,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器))
中文描述: 采用先進(jìn)的CMOS高速8位微控制器,集成8位CPU,內(nèi)存,光盤,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器(高速,先進(jìn)的的CMOS 8位微控制器(芯片集成了8位的CPU,ROM和RAM內(nèi)存,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器))
文件頁數(shù): 76/100頁
文件大?。?/td> 2591K
代理商: TMP90C401
76
TOSHIBA CORPORATION
TMP90C400/401
Serial clock generating circuit
This circuit generates the basic transmit/ receive clock.
1) I/O interface mode
It generates a clock at a 1/8 frequency (1.25Mbit/s at
10MHz) of the system clock (fc). This clock is output
from the SCLK pin (also used as P36).
2) Asynchronous communication (UART) mode
A basic clock (SIOCLK) is generated based on the
above baud rate generator clock, the internal clock 1
(fc/2) (SIOCLK = 5MHz, Transfer speed = 312.5Kb.p.s
at 10MHz). or the match signal from Timer 2, as
selected by SCMOD <SC1, 0> register.
Receiving counter
The receiving counter is a 4-bit binary counter used in
the asynchronous communication (UART) mode and is
counted by using SIOCLK. 16 pulse of SIOCLK is
used for receiving 1-bit data. The data are sampled
three timers a 7th, 8th and 9th pulses and evaluated
by the rule of majority. for example, if data sampled at
the 7th, 8th and 9th clock are “1”, “0” and “1”, the
received data is evaluated as “1”. The sampled data
“0”, “0” and “1” is evaluated that the received data is
“0”.
Receiving control
1) I/O interface mode
The RxD signal is sampled on the rising edge of the
shift clock which is output to the SCLK pin.
2) Asynchronous communication (UART) mode
The receiving control features a circuit for detecting the
start bit by the rule of majority. When two or more “0”
are detected during 3 samples, it is recognized as nor-
mal start bit and the receiving operation starts. Receiv-
ing data being received are also evaluated by the
majority logic while receiving data.
Receive buffer
The receive buffer has a double-buffer structure to prevent
overruns. Receive data are stored into the receive
buffer 1 (shift register type) for each 1 bit. When 7 or 8
bits data are stored in the receive buffer 1, the stored
data is transferred to the receive buffer 2 (SCBUF), and
the interrupt INTRX occurs at the same time. The CPU
reads out the receive buffer 2 (SCBUF). Data can be
stored into the receive buffer 1 before the CPU reads
out the receive buffer 2 (SCBUF).
Note, however, that an overrun occurs unless the CPU
reads out the receive buffer 2 (SCBUF) before the
receive buffer 1 receiving all bits of the next data.
When an overrun occurres, the data in the receive
buffer 2 and SCCR <RB8> are not lost, however, that
in the receive buffer 1 are lost.
SCCR <RB8> stores the MSB in the 9-bit UART
mode.
In the 9-bit UART mode, setting SCMOD <WU> to “1”
enables the wake-up function of the slave controllers, and
the interrupt INTRX occurs only if SCCR <RB8> = “1”.
Transmission counter
This is a 4-bit binary counter used in the asynchronous
communication (UART) mode. Like the receiving
counter, it counts based on SOICLK to generate a
transmission clock TXDCLK for every 16 counts.
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